* This has the disadvantage of not resetting the peripherals, so a
* reset-init event handler is needed to perform any peripheral resets.
*/
- retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
- AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
- ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
- if (retval != ERROR_OK)
- return retval;
-
LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
? "SYSRESETREQ" : "VECTRESET");
"handler to reset any peripherals or configure hardware srst support.");
}
- /*
- SAM4L needs to execute security initalization
- startup sequence before AP access would be enabled.
- During the intialization CDBGPWRUPACK is pulled low and we
- need to wait for it to be set to 1 again.
- */
- retval = dap_dp_poll_register(swjdp, DP_CTRL_STAT,
- CDBGPWRUPACK, CDBGPWRUPACK, 100);
+ retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+ AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
+ ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
+ if (retval != ERROR_OK)
+ LOG_DEBUG("Ignoring AP write error right after reset");
+
+ retval = ahbap_debugport_init(swjdp);
if (retval != ERROR_OK) {
- LOG_ERROR("Failed waitnig for CDBGPWRUPACK");
- return ERROR_FAIL;
+ LOG_ERROR("DP initialisation failed");
+ return retval;
}
{
/* deassert reset lines */
adapter_deassert_reset();
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+ if ((jtag_reset_config & RESET_HAS_SRST) &&
+ !(jtag_reset_config & RESET_SRST_NO_GATING)) {
+ int retval = ahbap_debugport_init(target_to_cm(target)->armv7m.arm.dap);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("DP initialisation failed");
+ return retval;
+ }
+ }
+
return ERROR_OK;
}
{
int retval;
int fp_num = 0;
- uint32_t hilo;
struct cortex_m_common *cortex_m = target_to_cm(target);
struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
if (breakpoint->type == BKPT_HARD) {
+ uint32_t fpcr_value;
while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
fp_num++;
if (fp_num >= cortex_m->fp_num_code) {
return ERROR_FAIL;
}
breakpoint->set = fp_num + 1;
- hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
+ fpcr_value = breakpoint->address | 1;
+ if (cortex_m->fp_rev == 0) {
+ uint32_t hilo;
+ hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
+ fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
+ } else if (cortex_m->fp_rev > 1) {
+ LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
+ return ERROR_FAIL;
+ }
comparator_list[fp_num].used = 1;
- comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
+ comparator_list[fp_num].fpcr_value = fpcr_value;
target_write_u32(target, comparator_list[fp_num].fpcr_address,
comparator_list[fp_num].fpcr_value);
LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
struct cortex_m_common *cortex_m = target_to_cm(target);
free(cortex_m->fp_comparator_list);
+
cortex_m_dwt_free(target);
+ armv7m_free_reg_cache(target);
+
free(cortex_m);
}
free(cm->dwt_comparator_list);
cm->dwt_comparator_list = NULL;
+ cm->dwt_num_comp = 0;
if (cache) {
register_unlink_cache(&target->reg_cache, cache);
armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
/* free unavailable FPU registers */
size_t idx;
+
for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
idx < armv7m->arm.core_cache->num_regs;
- idx++)
+ idx++) {
free(armv7m->arm.core_cache->reg_list[idx].value);
+ free(armv7m->arm.core_cache->reg_list[idx].feature);
+ free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
+ }
armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
}
cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
cortex_m->fp_code_available = cortex_m->fp_num_code;
+ /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
+ Revision is zero base, fp_rev == 1 means Rev.2 ! */
+ cortex_m->fp_rev = (fpcr >> 28) & 0xf;
free(cortex_m->fp_comparator_list);
cortex_m->fp_comparator_list = calloc(
cortex_m->fp_num_code + cortex_m->fp_num_lit,