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target/cortex_m: remove fp_code_available counting
[openocd.git] / src / target / cortex_m.c
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 07fea51374c1b2475b7810b904c4aee728bc1bd1..8c43016cbf04cdb3c11cdde13fe70d707475ce9f 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -265,7 +265,7 @@ static int cortex_m_endreset_event(struct target *target)
                return retval;
        }
 
-       cortex_m->fpb_enabled = 1;
+       cortex_m->fpb_enabled = true;
 
        /* Restore FPB registers */
        for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
@@ -510,7 +510,10 @@ static int cortex_m_poll(struct target *target)
        }
 
        if (cortex_m->dcb_dhcsr & S_RESET_ST) {
-               target->state = TARGET_RESET;
+               if (target->state != TARGET_RESET) {
+                       target->state = TARGET_RESET;
+                       LOG_INFO("%s: external reset detected", target_name(target));
+               }
                return ERROR_OK;
        }
 
@@ -564,6 +567,17 @@ static int cortex_m_poll(struct target *target)
                }
        }
 
+       /* Check that target is truly halted, since the target could be resumed externally */
+       if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
+               /* registers are now invalid */
+               register_cache_invalidate(armv7m->arm.core_cache);
+
+               target->state = TARGET_RUNNING;
+               LOG_WARNING("%s: external resume detected", target_name(target));
+               target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+               retval = ERROR_OK;
+       }
+
        /* Did we detect a failure condition that we cleared? */
        if (detected_failure != ERROR_OK)
                retval = detected_failure;
@@ -863,10 +877,17 @@ static int cortex_m_step(struct target *target, int current,
                        else {
 
                                /* Set a temporary break point */
-                               if (breakpoint)
+                               if (breakpoint) {
                                        retval = cortex_m_set_breakpoint(target, breakpoint);
-                               else
-                                       retval = breakpoint_add(target, pc_value, 2, BKPT_HARD);
+                               } else {
+                                       enum breakpoint_type type = BKPT_HARD;
+                                       if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
+                                               /* FPB rev.1 cannot handle such addr, try BKPT instr */
+                                               type = BKPT_SOFT;
+                                       }
+                                       retval = breakpoint_add(target, pc_value, 2, type);
+                               }
+
                                bool tmp_bp_set = (retval == ERROR_OK);
 
                                /* No more breakpoints left, just do a step */
@@ -1041,10 +1062,18 @@ static int cortex_m_assert_reset(struct target *target)
                retval = ERROR_OK;
        } else {
                /* Use a standard Cortex-M3 software reset mechanism.
-                * We default to using VECRESET as it is supported on all current cores.
+                * We default to using VECRESET as it is supported on all current cores
+                * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
                 * This has the disadvantage of not resetting the peripherals, so a
                 * reset-init event handler is needed to perform any peripheral resets.
                 */
+               if (!cortex_m->vectreset_supported
+                               && reset_config == CORTEX_M_RESET_VECTRESET) {
+                       reset_config = CORTEX_M_RESET_SYSRESETREQ;
+                       LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
+                       LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
+               }
+
                LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
                        ? "SYSRESETREQ" : "VECTRESET");
 
@@ -1135,7 +1164,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
                        fp_num++;
                if (fp_num >= cortex_m->fp_num_code) {
                        LOG_ERROR("Can not find free FPB Comparator!");
-                       return ERROR_FAIL;
+                       return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
                }
                breakpoint->set = fp_num + 1;
                fpcr_value = breakpoint->address | 1;
@@ -1151,7 +1180,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
                        LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
                        return ERROR_FAIL;
                }
-               comparator_list[fp_num].used = 1;
+               comparator_list[fp_num].used = true;
                comparator_list[fp_num].fpcr_value = fpcr_value;
                target_write_u32(target, comparator_list[fp_num].fpcr_address,
                        comparator_list[fp_num].fpcr_value);
@@ -1166,7 +1195,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
                                return retval;
                        }
 
-                       cortex_m->fpb_enabled = 1;
+                       cortex_m->fpb_enabled = true;
                }
        } else if (breakpoint->type == BKPT_SOFT) {
                uint8_t code[4];
@@ -1225,23 +1254,17 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
                        LOG_DEBUG("Invalid FP Comparator number in breakpoint");
                        return ERROR_OK;
                }
-               comparator_list[fp_num].used = 0;
+               comparator_list[fp_num].used = false;
                comparator_list[fp_num].fpcr_value = 0;
                target_write_u32(target, comparator_list[fp_num].fpcr_address,
                        comparator_list[fp_num].fpcr_value);
        } else {
                /* restore original instruction (kept in target endianness) */
-               if (breakpoint->length == 4) {
-                       retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
+               retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
+                                       breakpoint->length, 1,
                                        breakpoint->orig_instr);
-                       if (retval != ERROR_OK)
-                               return retval;
-               } else {
-                       retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
-                                       breakpoint->orig_instr);
-                       if (retval != ERROR_OK)
-                               return retval;
-               }
+               if (retval != ERROR_OK)
+                       return retval;
        }
        breakpoint->set = false;
 
@@ -1250,13 +1273,6 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
 
 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
-       struct cortex_m_common *cortex_m = target_to_cm(target);
-
-       if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
-               LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
-               return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-       }
-
        if (breakpoint->length == 3) {
                LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
                breakpoint->length = 2;
@@ -1267,16 +1283,11 @@ int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
 
-       if (breakpoint->type == BKPT_HARD)
-               cortex_m->fp_code_available--;
-
        return cortex_m_set_breakpoint(target, breakpoint);
 }
 
 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
-       struct cortex_m_common *cortex_m = target_to_cm(target);
-
        /* REVISIT why check? FPB can be updated with core running ... */
        if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
@@ -1286,9 +1297,6 @@ int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpo
        if (breakpoint->set)
                cortex_m_unset_breakpoint(target, breakpoint);
 
-       if (breakpoint->type == BKPT_HARD)
-               cortex_m->fp_code_available++;
-
        return ERROR_OK;
 }
 
@@ -1322,7 +1330,7 @@ int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint
                LOG_ERROR("Can not find free DWT Comparator");
                return ERROR_FAIL;
        }
-       comparator->used = 1;
+       comparator->used = true;
        watchpoint->set = dwt_num + 1;
 
        comparator->comp = watchpoint->address;
@@ -1379,7 +1387,7 @@ int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoi
        }
 
        comparator = cortex_m->dwt_comparator_list + dwt_num;
-       comparator->used = 0;
+       comparator->used = false;
        comparator->function = 0;
        target_write_u32(target, comparator->dwt_comparator_address + 8,
                comparator->function);
@@ -2027,6 +2035,9 @@ int cortex_m_examine(struct target *target)
                }
                LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
+               /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
+               cortex_m->vectreset_supported = i > 1;
+
                if (i == 4) {
                        target_read_u32(target, MVFR0, &mvfr0);
                        target_read_u32(target, MVFR1, &mvfr1);
@@ -2095,7 +2106,6 @@ int cortex_m_examine(struct target *target)
                /* bits [14:12] and [7:4] */
                cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
                cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
-               cortex_m->fp_code_available = cortex_m->fp_num_code;
                /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
                   Revision is zero base, fp_rev == 1 means Rev.2 ! */
                cortex_m->fp_rev = (fpcr >> 28) & 0xf;
@@ -2237,21 +2247,27 @@ static int cortex_m_init_arch_info(struct target *target,
        armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
        armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
 
-       target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
+       target_register_timer_callback(cortex_m_handle_target_request, 1,
+               TARGET_TIMER_TYPE_PERIODIC, target);
 
        return ERROR_OK;
 }
 
 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
 {
-       struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
-       cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
        struct adiv5_private_config *pc;
 
        pc = (struct adiv5_private_config *)target->private_config;
        if (adiv5_verify_config(pc) != ERROR_OK)
                return ERROR_FAIL;
 
+       struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
+       if (cortex_m == NULL) {
+               LOG_ERROR("No memory creating target");
+               return ERROR_FAIL;
+       }
+
+       cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
        cortex_m->apsel = pc->ap_num;
 
        cortex_m_init_arch_info(target, cortex_m, pc->dap);
@@ -2418,8 +2434,16 @@ COMMAND_HANDLER(handle_cortex_m_reset_config_command)
        if (CMD_ARGC > 0) {
                if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
                        cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
-               else if (strcmp(*CMD_ARGV, "vectreset") == 0)
-                       cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
+
+               else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
+                       if (target_was_examined(target)
+                                       && !cortex_m->vectreset_supported)
+                               LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
+                       else
+                               cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
+
+               } else
+                       return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        switch (cortex_m->soft_reset_config) {
@@ -2461,7 +2485,7 @@ static const struct command_registration cortex_m_exec_command_handlers[] = {
                .handler = handle_cortex_m_reset_config_command,
                .mode = COMMAND_ANY,
                .help = "configure software reset handling",
-               .usage = "['srst'|'sysresetreq'|'vectreset']",
+               .usage = "['sysresetreq'|'vectreset']",
        },
        COMMAND_REGISTRATION_DONE
 };
@@ -2499,6 +2523,7 @@ struct target_type cortexm_target = {
        .deassert_reset = cortex_m_deassert_reset,
        .soft_reset_halt = cortex_m_soft_reset_halt,
 
+       .get_gdb_arch = arm_get_gdb_arch,
        .get_gdb_reg_list = armv7m_get_gdb_reg_list,
 
        .read_memory = cortex_m_read_memory,
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