* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
* *
* *
* Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
uint32_t *value, int regnum)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
uint32_t dcrdr;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
if (target->dbg_msg_enabled) {
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, &dcrdr);
+ retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
if (retval != ERROR_OK)
return retval;
}
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRSR, regnum);
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, value);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
/* restore DCB_DCRDR - this needs to be in a separate
* transaction otherwise the emulated DCC channel breaks */
if (retval == ERROR_OK)
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, dcrdr);
+ retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
}
return retval;
uint32_t value, int regnum)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
uint32_t dcrdr;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
if (target->dbg_msg_enabled) {
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, &dcrdr);
+ retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
if (retval != ERROR_OK)
return retval;
}
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, value);
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
+ retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
if (retval == ERROR_OK)
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, dcrdr);
+ retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
}
return retval;
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
- struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
/* mask off status bits */
cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
/* create new register mask */
cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
- return mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
+ return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
}
static int cortex_m_clear_halt(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
- struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
int retval;
/* clear step if any */
cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
/* Read Debug Fault Status Register */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
/* Clear Debug Fault Status */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
+ retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
- struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
uint32_t dhcsr_save;
int retval;
* HALT can put the core into an unknown state.
*/
if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR,
+ retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR,
+ retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
/* REVISIT The four debug monitor bits are currently ignored... */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
/* this register is used for emulated dcc channel */
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, 0);
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
if (retval != ERROR_OK)
return retval;
/* Enable debug requests */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
* choices *EXCEPT* explicitly scripted overrides like "vector_catch"
* or manual updates to the NVIC SHCSR and CCR registers.
*/
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
if (retval != ERROR_OK)
return retval;
register_cache_invalidate(armv7m->arm.core_cache);
/* make sure we have latest dhcsr flags */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
return retval;
}
struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_SHCSR, &shcsr);
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
if (retval != ERROR_OK)
return retval;
switch (armv7m->exception_number) {
case 2: /* NMI */
break;
case 3: /* Hard Fault */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_HFSR, &except_sr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
if (except_sr & 0x40000000) {
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &cfsr);
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
if (retval != ERROR_OK)
return retval;
}
break;
case 4: /* Memory Management */
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &except_sr);
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_MMFAR, &except_ar);
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
if (retval != ERROR_OK)
return retval;
break;
case 5: /* Bus Fault */
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &except_sr);
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_BFAR, &except_ar);
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
if (retval != ERROR_OK)
return retval;
break;
case 6: /* Usage Fault */
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &except_sr);
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
- retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_DFSR, &except_sr);
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
break;
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct arm *arm = &armv7m->arm;
- struct adiv5_dap *swjdp = armv7m->arm.dap;
struct reg *r;
LOG_DEBUG(" ");
cortex_m_clear_halt(target);
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
enum target_state prev_target_state = target->state;
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
- struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
/* Read from Debug Halting Control and Status Register */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK) {
target->state = TARGET_UNKNOWN;
return retval;
detected_failure = ERROR_FAIL;
/* refresh status bits */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
}
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
- struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
/* Enter debug state on reset; restore DEMCR in endreset_event() */
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
if (retval != ERROR_OK)
return retval;
/* Request a core-only reset */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, NVIC_AIRCR,
+ retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
AIRCR_VECTKEY | AIRCR_VECTRESET);
if (retval != ERROR_OK)
return retval;
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
while (timeout < 100) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
if (retval == ERROR_OK) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_DFSR,
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
&cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
- struct adiv5_dap *swjdp = armv7m->arm.dap;
struct breakpoint *breakpoint = NULL;
struct reg *pc = armv7m->arm.pc;
bool bkpt_inst_found = false;
/* Wait for pending handlers to complete or timeout */
do {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
DCB_DHCSR,
&cortex_m->dcb_dhcsr);
if (retval != ERROR_OK) {
}
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
- struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
LOG_DEBUG("target->state: %s",
/* Enable debug requests */
int retval;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
- if (retval != ERROR_OK)
- return retval;
- if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
- if (retval != ERROR_OK)
- return retval;
- }
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ /* Store important errors instead of failing and proceed to reset assert */
+
+ if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
/* If the processor is sleeping in a WFI or WFE instruction, the
* C_HALT bit must be asserted to regain control */
- if (cortex_m->dcb_dhcsr & S_SLEEP) {
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
- if (retval != ERROR_OK)
- return retval;
- }
+ if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, 0);
- if (retval != ERROR_OK)
- return retval;
+ mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
+ /* Ignore less important errors */
if (!target->reset_halt) {
/* Set/Clear C_MASKINTS in a separate operation */
- if (cortex_m->dcb_dhcsr & C_MASKINTS) {
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR,
+ if (cortex_m->dcb_dhcsr & C_MASKINTS)
+ mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_DEBUGEN | C_HALT);
- if (retval != ERROR_OK)
- return retval;
- }
/* clear any debug flags before resuming */
cortex_m_clear_halt(target);
* bad vector table entries. Should this include MMERR or
* other flags too?
*/
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
+ int retval2;
+ retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
- if (retval != ERROR_OK)
- return retval;
+ if (retval != ERROR_OK || retval2 != ERROR_OK)
+ LOG_INFO("AP write error, reset will not halt");
}
if (jtag_reset_config & RESET_HAS_SRST) {
/* default to asserting srst */
if (!srst_asserted)
adapter_assert_reset();
+
+ /* srst is asserted, ignore AP access errors */
+ retval = ERROR_OK;
} else {
/* Use a standard Cortex-M3 software reset mechanism.
* We default to using VECRESET as it is supported on all current cores.
"handler to reset any peripherals or configure hardware srst support.");
}
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, NVIC_AIRCR,
+ int retval3;
+ retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
- if (retval != ERROR_OK)
+ if (retval3 != ERROR_OK)
LOG_DEBUG("Ignoring AP write error right after reset");
- retval = ahbap_debugport_init(swjdp, armv7m->debug_ap);
- if (retval != ERROR_OK) {
+ retval3 = dap_dp_init(armv7m->debug_ap->dap);
+ if (retval3 != ERROR_OK)
LOG_ERROR("DP initialisation failed");
- return retval;
- }
- {
+ else {
/* I do not know why this is necessary, but it
* fixes strange effects (step/resume cause NMI
* after reset) on LM3S6918 -- Michael Schwingen
*/
uint32_t tmp;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_AIRCR, &tmp);
- if (retval != ERROR_OK)
- return retval;
+ mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
}
}
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
+ /* now return stored error code if any */
+ if (retval != ERROR_OK)
+ return retval;
+
if (target->reset_halt) {
retval = target_halt(target);
if (retval != ERROR_OK)
if ((jtag_reset_config & RESET_HAS_SRST) &&
!(jtag_reset_config & RESET_SRST_NO_GATING)) {
- int retval = ahbap_debugport_init(armv7m->arm.dap, armv7m->debug_ap);
+ int retval = dap_dp_init(armv7m->debug_ap->dap);
if (retval != ERROR_OK) {
LOG_ERROR("DP initialisation failed");
return retval;
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = armv7m->arm.dap;
if (armv7m->arm.is_armv6m) {
/* armv6m does not handle unaligned memory access */
return ERROR_TARGET_UNALIGNED_ACCESS;
}
- return mem_ap_sel_read_buf(swjdp, armv7m->debug_ap, buffer, size, count, address);
+ return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
}
static int cortex_m_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = armv7m->arm.dap;
if (armv7m->arm.is_armv6m) {
/* armv6m does not handle unaligned memory access */
return ERROR_TARGET_UNALIGNED_ACCESS;
}
- return mem_ap_sel_write_buf(swjdp, armv7m->debug_ap, buffer, size, count, address);
+ return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
}
static int cortex_m_init_target(struct command_context *cmd_ctx,
#define MVFR0_DEFAULT_M4 0x10110021
#define MVFR1_DEFAULT_M4 0x11000011
+#define MVFR0_DEFAULT_M7_SP 0x10110021
+#define MVFR0_DEFAULT_M7_DP 0x10110221
+#define MVFR1_DEFAULT_M7_SP 0x11000011
+#define MVFR1_DEFAULT_M7_DP 0x12000011
+
int cortex_m_examine(struct target *target)
{
int retval;
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
struct armv7m_common *armv7m = target_to_armv7m(target);
- /* Leave (only) generic DAP stuff for debugport_init(); */
- swjdp->ap[armv7m->debug_ap].memaccess_tck = 8;
-
/* stlink shares the examine handler but does not support
* all its calls */
if (!armv7m->stlink) {
- retval = ahbap_debugport_init(swjdp, armv7m->debug_ap);
+ retval = dap_dp_init(swjdp);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not initialize the debug port");
+ return retval;
+ }
+
+ /* Search for the MEM-AP */
+ retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not find MEM-AP to control the core");
+ return retval;
+ }
+
+ /* Leave (only) generic DAP stuff for debugport_init(); */
+ armv7m->debug_ap->memaccess_tck = 8;
+
+ retval = mem_ap_init(armv7m->debug_ap);
if (retval != ERROR_OK)
return retval;
}
LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
+ if (i == 7) {
+ uint8_t rev, patch;
+ rev = (cpuid >> 20) & 0xf;
+ patch = (cpuid >> 0) & 0xf;
+ if ((rev == 0) && (patch < 2))
+ LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
+ }
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
- /* test for floating point feature on cortex-m4 */
if (i == 4) {
target_read_u32(target, MVFR0, &mvfr0);
target_read_u32(target, MVFR1, &mvfr1);
+ /* test for floating point feature on Cortex-M4 */
if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
armv7m->fp_feature = FPv4_SP;
}
+ } else if (i == 7) {
+ target_read_u32(target, MVFR0, &mvfr0);
+ target_read_u32(target, MVFR1, &mvfr1);
+
+ /* test for floating point features on Cortex-M7 */
+ if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
+ LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
+ armv7m->fp_feature = FPv5_SP;
+ } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
+ LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
+ armv7m->fp_feature = FPv5_DP;
+ }
} else if (i == 0) {
/* Cortex-M0 does not support unaligned memory access */
armv7m->arm.is_armv6m = true;
}
- if (armv7m->fp_feature != FPv4_SP &&
+ if (armv7m->fp_feature == FP_NONE &&
armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
/* free unavailable FPU registers */
size_t idx;
armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
}
- if (i == 4 || i == 3) {
- /* Cortex-M3/M4 has 4096 bytes autoincrement range */
- swjdp->ap[armv7m->debug_ap].tar_autoincr_block = (1 << 12);
+ if ((i == 3 || i == 4 || i == 7) && !armv7m->stlink) {
+ /* Cortex-M3/M4/M7 have at least 4096 bytes autoincrement range,
+ * s. ARM IHI 0031C: MEM-AP 7.2.2 */
+ armv7m->debug_ap->tar_autoincr_block = (1 << 12);
}
/* Configure trace modules */
static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = armv7m->arm.dap;
uint16_t dcrdr;
uint8_t buf[2];
int retval;
- retval = mem_ap_sel_read_buf_noincr(swjdp, armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
+ retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
if (retval != ERROR_OK)
return retval;
* signify we have read data */
if (dcrdr & (1 << 0)) {
target_buffer_set_u16(target, buf, 0);
- retval = mem_ap_sel_write_buf_noincr(swjdp, armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
+ retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
if (retval != ERROR_OK)
return retval;
}
armv7m->arm.dap = tap->dap;
- /* Leave (only) generic DAP stuff for debugport_init(); */
- tap->dap->ap[dap_ap_get_select(tap->dap)].memaccess_tck = 8;
-
/* register arch-specific functions */
armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
struct target *target = get_current_target(CMD_CTX);
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
- struct adiv5_dap *swjdp = armv7m->arm.dap;
uint32_t demcr = 0;
int retval;
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, &demcr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
if (retval != ERROR_OK)
return retval;
demcr |= catch;
/* write, but don't assume it stuck (why not??) */
- retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, demcr);
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, &demcr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
if (retval != ERROR_OK)
return retval;
Code Review / openocd.git / blobdiff