#include "config.h"
#endif
+#include "jtag/interface.h"
#include "breakpoints.h"
#include "cortex_m.h"
#include "target_request.h"
/* forward declarations */
-static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
-static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
-static void cortex_m3_enable_watchpoints(struct target *target);
static int cortex_m3_store_core_reg_u32(struct target *target,
- enum armv7m_regtype type, uint32_t num, uint32_t value);
+ uint32_t num, uint32_t value);
static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
- uint32_t *value, int regnum)
+ uint32_t *value, int regnum)
{
int retval;
uint32_t dcrdr;
}
static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
- uint32_t value, int regnum)
+ uint32_t value, int regnum)
{
int retval;
uint32_t dcrdr;
}
static int cortex_m3_write_debug_halt_mask(struct target *target,
- uint32_t mask_on, uint32_t mask_off)
+ uint32_t mask_on, uint32_t mask_off)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
static int cortex_m3_clear_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
int retval;
/* clear step if any */
static int cortex_m3_single_step_core(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
uint32_t dhcsr_save;
int retval;
* Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
* HALT can put the core into an unknown state.
*/
- if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
- {
+ if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) {
retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
- DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
+ DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG(" ");
uint32_t dcb_demcr;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
+ LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
/* this register is used for emulated dcc channel */
retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
- if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- {
+ if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) {
retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
cortex_m3->fpb_enabled = 1;
/* Restore FPB registers */
- for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
- {
+ for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) {
retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
if (retval != ERROR_OK)
return retval;
}
/* Restore DWT registers */
- for (i = 0; i < cortex_m3->dwt_num_comp; i++)
- {
+ for (i = 0; i < cortex_m3->dwt_num_comp; i++) {
retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
dwt_list[i].comp);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
return retval;
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(armv7m->arm.core_cache);
/* make sure we have latest dhcsr flags */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
- /* only check the debug reason if we don't know it already */
+ /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
+ * only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
- && (target->debug_reason != DBG_REASON_SINGLESTEP))
- {
- if (cortex_m3->nvic_dfsr & DFSR_BKPT)
- {
+ && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
+ if (cortex_m3->nvic_dfsr & DFSR_BKPT) {
target->debug_reason = DBG_REASON_BREAKPOINT;
if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
target->debug_reason = DBG_REASON_WPTANDBKPT;
- }
- else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
+ } else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
target->debug_reason = DBG_REASON_WATCHPOINT;
else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
target->debug_reason = DBG_REASON_BREAKPOINT;
- else /* EXTERNAL, HALTED */
+ else /* EXTERNAL, HALTED */
target->debug_reason = DBG_REASON_UNDEFINED;
}
{
uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
if (retval != ERROR_OK)
return retval;
- switch (armv7m->exception_number)
- {
+ switch (armv7m->exception_number) {
case 2: /* NMI */
break;
case 3: /* Hard Fault */
retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
- if (except_sr & 0x40000000)
- {
+ if (except_sr & 0x40000000) {
retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
if (retval != ERROR_OK)
return retval;
return retval;
}
-/* PSP is used in some thread modes */
-static const int armv7m_psp_reg_map[17] = {
- ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
- ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
- ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
- ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
- ARMV7M_xPSR,
-};
-
-/* MSP is used in handler and some thread modes */
-static const int armv7m_msp_reg_map[17] = {
- ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
- ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
- ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
- ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
- ARMV7M_xPSR,
-};
-
static int cortex_m3_debug_entry(struct target *target)
{
int i;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
struct arm *arm = &armv7m->arm;
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
struct reg *r;
LOG_DEBUG(" ");
if (retval != ERROR_OK)
return retval;
- if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
+ retval = armv7m->examine_debug_reason(target);
+ if (retval != ERROR_OK)
return retval;
- /* Examine target state and mode */
- /* First load register acessible through core debug port*/
- int num_regs = armv7m->core_cache->num_regs;
+ /* Examine target state and mode
+ * First load register accessible through core debug port */
+ int num_regs = arm->core_cache->num_regs;
- for (i = 0; i < num_regs; i++)
- {
- if (!armv7m->core_cache->reg_list[i].valid)
- armv7m->read_core_reg(target, i);
+ for (i = 0; i < num_regs; i++) {
+ r = &armv7m->arm.core_cache->reg_list[i];
+ if (!r->valid)
+ arm->read_core_reg(target, r, i, ARM_MODE_ANY);
}
- r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
+ r = arm->core_cache->reg_list + ARMV7M_xPSR;
xPSR = buf_get_u32(r->value, 0, 32);
#ifdef ARMV7_GDB_HACKS
#endif
/* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
- if (xPSR & 0xf00)
- {
+ if (xPSR & 0xf00) {
r->dirty = r->valid;
- cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
+ cortex_m3_store_core_reg_u32(target, 16, xPSR & ~0xff);
}
/* Are we in an exception handler */
- if (xPSR & 0x1FF)
- {
- armv7m->core_mode = ARMV7M_MODE_HANDLER;
+ if (xPSR & 0x1FF) {
armv7m->exception_number = (xPSR & 0x1FF);
arm->core_mode = ARM_MODE_HANDLER;
arm->map = armv7m_msp_reg_map;
- }
- else
- {
- unsigned control = buf_get_u32(armv7m->core_cache
+ } else {
+ unsigned control = buf_get_u32(arm->core_cache
->reg_list[ARMV7M_CONTROL].value, 0, 2);
/* is this thread privileged? */
- armv7m->core_mode = control & 1;
- arm->core_mode = armv7m->core_mode
- ? ARM_MODE_USER_THREAD
- : ARM_MODE_THREAD;
+ arm->core_mode = control & 1
+ ? ARM_MODE_USER_THREAD
+ : ARM_MODE_THREAD;
/* which stack is it using? */
if (control & 2)
}
if (armv7m->exception_number)
- {
cortex_m3_examine_exception_reason(target);
- }
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
- armv7m_mode_strings[armv7m->core_mode],
- *(uint32_t*)(arm->pc->value),
+ arm_mode_name(arm->core_mode),
+ *(uint32_t *)(arm->pc->value),
target_state_name(target));
- if (armv7m->post_debug_entry)
- {
+ if (armv7m->post_debug_entry) {
retval = armv7m->post_debug_entry(target);
if (retval != ERROR_OK)
return retval;
int retval = ERROR_OK;
enum target_state prev_target_state = target->state;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
/* Read from Debug Halting Control and Status Register */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
- if (retval != ERROR_OK)
- {
+ if (retval != ERROR_OK) {
target->state = TARGET_UNKNOWN;
return retval;
}
*/
if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
LOG_ERROR("%s -- clearing lockup after double fault",
- target_name(target));
+ target_name(target));
cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
target->debug_reason = DBG_REASON_DBGRQ;
return retval;
}
- if (cortex_m3->dcb_dhcsr & S_RESET_ST)
- {
+ if (cortex_m3->dcb_dhcsr & S_RESET_ST) {
/* check if still in reset */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
- if (cortex_m3->dcb_dhcsr & S_RESET_ST)
- {
+ if (cortex_m3->dcb_dhcsr & S_RESET_ST) {
target->state = TARGET_RESET;
return ERROR_OK;
}
}
- if (target->state == TARGET_RESET)
- {
+ if (target->state == TARGET_RESET) {
/* Cannot switch context while running so endreset is
* called with target->state == TARGET_RESET
*/
LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
- cortex_m3->dcb_dhcsr);
+ cortex_m3->dcb_dhcsr);
cortex_m3_endreset_event(target);
target->state = TARGET_RUNNING;
prev_target_state = TARGET_RUNNING;
}
- if (cortex_m3->dcb_dhcsr & S_HALT)
- {
+ if (cortex_m3->dcb_dhcsr & S_HALT) {
target->state = TARGET_HALTED;
- if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
- {
- if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
+ if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
+ retval = cortex_m3_debug_entry(target);
+ if (retval != ERROR_OK)
return retval;
if (arm_semihosting(target, &retval) != 0)
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
- if (prev_target_state == TARGET_DEBUG_RUNNING)
- {
+ if (prev_target_state == TARGET_DEBUG_RUNNING) {
LOG_DEBUG(" ");
- if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
+ retval = cortex_m3_debug_entry(target);
+ if (retval != ERROR_OK)
return retval;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
* How best to model low power modes?
*/
- if (target->state == TARGET_UNKNOWN)
- {
+ if (target->state == TARGET_UNKNOWN) {
/* check if processor is retiring instructions */
- if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
- {
+ if (cortex_m3->dcb_dhcsr & S_RETIRE_ST) {
target->state = TARGET_RUNNING;
retval = ERROR_OK;
}
LOG_DEBUG("target->state: %s",
target_state_name(target));
- if (target->state == TARGET_HALTED)
- {
+ if (target->state == TARGET_HALTED) {
LOG_DEBUG("target was already halted");
return ERROR_OK;
}
if (target->state == TARGET_UNKNOWN)
- {
LOG_WARNING("target was in unknown state when halt was requested");
- }
- if (target->state == TARGET_RESET)
- {
- if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
- {
+ if (target->state == TARGET_RESET) {
+ if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
- }
- else
- {
+ } else {
/* we came here in a reset_halt or reset_init sequence
- * debug entry was already prepared in cortex_m3_prepare_reset_halt()
+ * debug entry was already prepared in cortex_m3_assert_reset()
*/
target->debug_reason = DBG_REASON_DBGRQ;
static int cortex_m3_soft_reset_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
target->state = TARGET_RESET;
/* registers are now invalid */
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(cortex_m3->armv7m.arm.core_cache);
- while (timeout < 100)
- {
+ while (timeout < 100) {
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
- if (retval == ERROR_OK)
- {
+ if (retval == ERROR_OK) {
retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
&cortex_m3->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
if ((dcb_dhcsr & S_HALT)
- && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
- {
+ && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) {
LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
"DFSR 0x%08x",
(unsigned) dcb_dhcsr,
cortex_m3_poll(target);
/* FIXME restore user's vector catch config */
return ERROR_OK;
- }
- else
+ } else
LOG_DEBUG("waiting for system reset-halt, "
"DHCSR 0x%08x, %d ms",
(unsigned) dcb_dhcsr, timeout);
return ERROR_OK;
}
-static void cortex_m3_enable_breakpoints(struct target *target)
+void cortex_m3_enable_breakpoints(struct target *target)
{
struct breakpoint *breakpoint = target->breakpoints;
/* set any pending breakpoints */
- while (breakpoint)
- {
+ while (breakpoint) {
if (!breakpoint->set)
cortex_m3_set_breakpoint(target, breakpoint);
breakpoint = breakpoint->next;
}
static int cortex_m3_resume(struct target *target, int current,
- uint32_t address, int handle_breakpoints, int debug_execution)
+ uint32_t address, int handle_breakpoints, int debug_execution)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct breakpoint *breakpoint = NULL;
uint32_t resume_pc;
struct reg *r;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (!debug_execution)
- {
+ if (!debug_execution) {
target_free_all_working_areas(target);
cortex_m3_enable_breakpoints(target);
cortex_m3_enable_watchpoints(target);
}
- if (debug_execution)
- {
- r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
+ if (debug_execution) {
+ r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
/* Disable interrupts */
/* We disable interrupts in the PRIMASK register instead of
r->valid = true;
/* Make sure we are in Thumb mode */
- r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
+ r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR;
buf_set_u32(r->value, 24, 1, 1);
r->dirty = true;
r->valid = true;
/* current = 1: continue on current pc, otherwise continue at <address> */
r = armv7m->arm.pc;
- if (!current)
- {
+ if (!current) {
buf_set_u32(r->value, 0, 32, address);
r->dirty = true;
r->valid = true;
* the core will break again */
if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
- && !debug_execution)
- {
+ && !debug_execution)
armv7m_maybe_skip_bkpt_inst(target, NULL);
- }
resume_pc = buf_get_u32(r->value, 0, 32);
armv7m_restore_context(target);
/* the front-end may request us not to handle breakpoints */
- if (handle_breakpoints)
- {
+ if (handle_breakpoints) {
/* Single step past breakpoint at current address */
- if ((breakpoint = breakpoint_find(target, resume_pc)))
- {
+ breakpoint = breakpoint_find(target, resume_pc);
+ if (breakpoint) {
LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
- breakpoint->address,
- breakpoint->unique_id);
+ breakpoint->address,
+ breakpoint->unique_id);
cortex_m3_unset_breakpoint(target, breakpoint);
cortex_m3_single_step_core(target);
cortex_m3_set_breakpoint(target, breakpoint);
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
- register_cache_invalidate(armv7m->core_cache);
+ register_cache_invalidate(armv7m->arm.core_cache);
- if (!debug_execution)
- {
+ if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
- }
- else
- {
+ } else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
/* int irqstepcount = 0; */
static int cortex_m3_step(struct target *target, int current,
- uint32_t address, int handle_breakpoints)
+ uint32_t address, int handle_breakpoints)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
struct breakpoint *breakpoint = NULL;
struct reg *pc = armv7m->arm.pc;
bool bkpt_inst_found = false;
int retval;
bool isr_timed_out = false;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* if no bkpt instruction is found at pc then we can perform
* a normal step, otherwise we have to manually step over the bkpt
* instruction - as such simulate a step */
- if (bkpt_inst_found == false)
- {
+ if (bkpt_inst_found == false) {
/* Automatic ISR masking mode off: Just step over the next instruction */
if ((cortex_m3->isrmasking_mode != CORTEX_M3_ISRMASK_AUTO))
- {
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
- }
- else
- {
+ else {
/* Process interrupts during stepping in a way they don't interfere
* debugging.
*
*
*/
- /* Set a temporary break point */
- retval = breakpoint_add(target, pc_value , 2, BKPT_TYPE_BY_ADDR(pc_value));
- bool tmp_bp_set = (retval == ERROR_OK);
-
- /* No more breakpoints left, just do a step */
- if (!tmp_bp_set)
- {
+ /* 2012-09-29 ph
+ *
+ * If a break point is already set on the lower half word then a break point on
+ * the upper half word will not break again when the core is restarted. So we
+ * just step over the instruction with interrupts disabled.
+ *
+ * The documentation has no information about this, it was found by observation
+ * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
+ * suffer from this problem.
+ *
+ * To add some confusion: pc_value has bit 0 always set, while the breakpoint
+ * address has it always cleared. The former is done to indicate thumb mode
+ * to gdb.
+ *
+ */
+ if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
+ LOG_DEBUG("Stepping over next instruction with interrupts disabled");
+ cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+ /* Re-enable interrupts */
+ cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
}
- else
- {
- /* Start the core */
- LOG_DEBUG("Starting core to serve pending interrupts");
- int64_t t_start = timeval_ms();
- cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
-
- /* Wait for pending handlers to complete or timeout */
- do {
- retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
- if (retval != ERROR_OK)
- {
- target->state = TARGET_UNKNOWN;
- return retval;
- }
- isr_timed_out = ((timeval_ms() - t_start) > 500);
- } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
-
- /* Remove the temporary breakpoint */
- breakpoint_remove(target, pc_value);
+ else {
- if (isr_timed_out)
- {
- LOG_DEBUG("Interrupt handlers didn't complete within time, "
- "leaving target running");
- }
+ /* Set a temporary break point */
+ if (breakpoint)
+ retval = cortex_m3_set_breakpoint(target, breakpoint);
else
- {
- /* Step over next instruction with interrupts disabled */
- cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
+ retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
+ bool tmp_bp_set = (retval == ERROR_OK);
+
+ /* No more breakpoints left, just do a step */
+ if (!tmp_bp_set)
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
- /* Re-enable interrupts */
- cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+ else {
+ /* Start the core */
+ LOG_DEBUG("Starting core to serve pending interrupts");
+ int64_t t_start = timeval_ms();
+ cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
+
+ /* Wait for pending handlers to complete or timeout */
+ do {
+ retval = mem_ap_read_atomic_u32(swjdp,
+ DCB_DHCSR,
+ &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK) {
+ target->state = TARGET_UNKNOWN;
+ return retval;
+ }
+ isr_timed_out = ((timeval_ms() - t_start) > 500);
+ } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
+
+ /* only remove breakpoint if we created it */
+ if (breakpoint)
+ cortex_m3_unset_breakpoint(target, breakpoint);
+ else {
+ /* Remove the temporary breakpoint */
+ breakpoint_remove(target, pc_value);
+ }
+
+ if (isr_timed_out) {
+ LOG_DEBUG("Interrupt handlers didn't complete within time, "
+ "leaving target running");
+ } else {
+ /* Step over next instruction with interrupts disabled */
+ cortex_m3_write_debug_halt_mask(target,
+ C_HALT | C_MASKINTS,
+ 0);
+ cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+ /* Re-enable interrupts */
+ cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+ }
}
}
}
return retval;
/* registers are now invalid */
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(armv7m->arm.core_cache);
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
}
LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
- " nvic_icsr = 0x%" PRIx32,
- cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
+ " nvic_icsr = 0x%" PRIx32,
+ cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
retval = cortex_m3_debug_entry(target);
if (retval != ERROR_OK)
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
- " nvic_icsr = 0x%" PRIx32,
- cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
+ " nvic_icsr = 0x%" PRIx32,
+ cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
return ERROR_OK;
}
static int cortex_m3_assert_reset(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
LOG_DEBUG("target->state: %s",
/* allow scripts to override the reset event */
target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(cortex_m3->armv7m.arm.core_cache);
target->state = TARGET_RESET;
return ERROR_OK;
}
+ /* some cores support connecting while srst is asserted
+ * use that mode is it has been configured */
+
+ bool srst_asserted = false;
+
+ if (jtag_reset_config & RESET_SRST_NO_GATING) {
+ adapter_assert_reset();
+ srst_asserted = true;
+ }
+
/* Enable debug requests */
int retval;
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
- if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- {
+ if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) {
retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
+ /* If the processor is sleeping in a WFI or WFE instruction, the
+ * C_HALT bit must be asserted to regain control */
+ if (cortex_m3->dcb_dhcsr & S_SLEEP) {
+ retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
if (retval != ERROR_OK)
return retval;
- if (!target->reset_halt)
- {
+ if (!target->reset_halt) {
/* Set/Clear C_MASKINTS in a separate operation */
- if (cortex_m3->dcb_dhcsr & C_MASKINTS)
- {
+ if (cortex_m3->dcb_dhcsr & C_MASKINTS) {
retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
DBGKEY | C_DEBUGEN | C_HALT);
if (retval != ERROR_OK)
/* clear C_HALT in dhcsr reg */
cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
- }
- else
- {
+ } else {
/* Halt in debug on reset; endreset_event() restores DEMCR.
*
* REVISIT catching BUSERR presumably helps to defend against
return retval;
}
- if (jtag_reset_config & RESET_HAS_SRST)
- {
+ if (jtag_reset_config & RESET_HAS_SRST) {
/* default to asserting srst */
- if (jtag_reset_config & RESET_SRST_PULLS_TRST)
- {
- jtag_add_reset(1, 1);
- }
- else
- {
- jtag_add_reset(0, 1);
- }
- }
- else
- {
+ if (!srst_asserted)
+ adapter_assert_reset();
+ } else {
/* Use a standard Cortex-M3 software reset mechanism.
* We default to using VECRESET as it is supported on all current cores.
* This has the disadvantage of not resetting the peripherals, so a
return retval;
LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
- ? "SYSRESETREQ" : "VECTRESET");
+ ? "SYSRESETREQ" : "VECTRESET");
if (reset_config == CORTEX_M3_RESET_VECTRESET) {
LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
- "handler to reset any peripherals");
+ "handler to reset any peripherals or configure hardware srst support.");
}
{
target->state = TARGET_RESET;
jtag_add_sleep(50000);
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(cortex_m3->armv7m.arm.core_cache);
- if (target->reset_halt)
- {
- if ((retval = target_halt(target)) != ERROR_OK)
+ if (target->reset_halt) {
+ retval = target_halt(target);
+ if (retval != ERROR_OK)
return retval;
}
target_state_name(target));
/* deassert reset lines */
- jtag_add_reset(0, 0);
+ adapter_deassert_reset();
return ERROR_OK;
}
-static int
-cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
+int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
int fp_num = 0;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
- if (breakpoint->set)
- {
+ if (breakpoint->set) {
LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
return ERROR_OK;
}
if (cortex_m3->auto_bp_type)
- {
breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
- }
- if (breakpoint->type == BKPT_HARD)
- {
+ if (breakpoint->type == BKPT_HARD) {
while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
fp_num++;
- if (fp_num >= cortex_m3->fp_num_code)
- {
+ if (fp_num >= cortex_m3->fp_num_code) {
LOG_ERROR("Can not find free FPB Comparator!");
return ERROR_FAIL;
}
hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
comparator_list[fp_num].used = 1;
comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
- target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
- LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
- if (!cortex_m3->fpb_enabled)
- {
+ target_write_u32(target, comparator_list[fp_num].fpcr_address,
+ comparator_list[fp_num].fpcr_value);
+ LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
+ fp_num,
+ comparator_list[fp_num].fpcr_value);
+ if (!cortex_m3->fpb_enabled) {
LOG_DEBUG("FPB wasn't enabled, do it now");
target_write_u32(target, FP_CTRL, 3);
}
- }
- else if (breakpoint->type == BKPT_SOFT)
- {
+ } else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
/* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
}
LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
- breakpoint->unique_id,
- (int)(breakpoint->type),
- breakpoint->address,
- breakpoint->length,
- breakpoint->set);
+ breakpoint->unique_id,
+ (int)(breakpoint->type),
+ breakpoint->address,
+ breakpoint->length,
+ breakpoint->set);
return ERROR_OK;
}
-static int
-cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
+int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
+ struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
- if (!breakpoint->set)
- {
+ if (!breakpoint->set) {
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
- breakpoint->unique_id,
- (int)(breakpoint->type),
- breakpoint->address,
- breakpoint->length,
- breakpoint->set);
+ breakpoint->unique_id,
+ (int)(breakpoint->type),
+ breakpoint->address,
+ breakpoint->length,
+ breakpoint->set);
- if (breakpoint->type == BKPT_HARD)
- {
+ if (breakpoint->type == BKPT_HARD) {
int fp_num = breakpoint->set - 1;
- if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
- {
+ if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code)) {
LOG_DEBUG("Invalid FP Comparator number in breakpoint");
return ERROR_OK;
}
comparator_list[fp_num].used = 0;
comparator_list[fp_num].fpcr_value = 0;
- target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
- }
- else
- {
+ target_write_u32(target, comparator_list[fp_num].fpcr_address,
+ comparator_list[fp_num].fpcr_value);
+ } else {
/* restore original instruction (kept in target endianness) */
- if (breakpoint->length == 4)
- {
- if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
- {
+ if (breakpoint->length == 4) {
+ retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
+ breakpoint->orig_instr);
+ if (retval != ERROR_OK)
return retval;
- }
- }
- else
- {
- if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
- {
+ } else {
+ retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
+ breakpoint->orig_instr);
+ if (retval != ERROR_OK)
return retval;
- }
}
}
breakpoint->set = false;
return ERROR_OK;
}
-static int
-cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
+int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- if (cortex_m3->auto_bp_type)
- {
+ if (cortex_m3->auto_bp_type) {
breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
#ifdef ARMV7_GDB_HACKS
if (breakpoint->length != 2) {
#endif
}
- if(breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
- if (breakpoint->type == BKPT_HARD)
- {
+ if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
+ if (breakpoint->type == BKPT_HARD) {
LOG_INFO("flash patch comparator requested outside code memory region");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- if (breakpoint->type == BKPT_SOFT)
- {
+ if (breakpoint->type == BKPT_SOFT) {
LOG_INFO("soft breakpoint requested in code (flash) memory region");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
- if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
- {
+ if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1)) {
LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- if ((breakpoint->length != 2))
- {
+ if ((breakpoint->length != 2)) {
LOG_INFO("only breakpoints of two bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
return cortex_m3_set_breakpoint(target, breakpoint);
}
-static int
-cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
+int cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* REVISIT why check? FBP can be updated with core running ... */
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (cortex_m3->auto_bp_type)
- {
breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
- }
if (breakpoint->set)
- {
cortex_m3_unset_breakpoint(target, breakpoint);
- }
if (breakpoint->type == BKPT_HARD)
cortex_m3->fp_code_available++;
return ERROR_OK;
}
-static int
-cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
+int cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int dwt_num = 0;
uint32_t mask, temp;
struct cortex_m3_dwt_comparator *comparator;
for (comparator = cortex_m3->dwt_comparator_list;
- comparator->used && dwt_num < cortex_m3->dwt_num_comp;
- comparator++, dwt_num++)
+ comparator->used && dwt_num < cortex_m3->dwt_num_comp;
+ comparator++, dwt_num++)
continue;
- if (dwt_num >= cortex_m3->dwt_num_comp)
- {
+ if (dwt_num >= cortex_m3->dwt_num_comp) {
LOG_ERROR("Can not find free DWT Comparator");
return ERROR_FAIL;
}
comparator->comp = watchpoint->address;
target_write_u32(target, comparator->dwt_comparator_address + 0,
- comparator->comp);
+ comparator->comp);
comparator->mask = mask;
target_write_u32(target, comparator->dwt_comparator_address + 4,
- comparator->mask);
+ comparator->mask);
switch (watchpoint->rw) {
- case WPT_READ:
- comparator->function = 5;
- break;
- case WPT_WRITE:
- comparator->function = 6;
- break;
- case WPT_ACCESS:
- comparator->function = 7;
- break;
+ case WPT_READ:
+ comparator->function = 5;
+ break;
+ case WPT_WRITE:
+ comparator->function = 6;
+ break;
+ case WPT_ACCESS:
+ comparator->function = 7;
+ break;
}
target_write_u32(target, comparator->dwt_comparator_address + 8,
- comparator->function);
+ comparator->function);
LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
- watchpoint->unique_id, dwt_num,
- (unsigned) comparator->comp,
- (unsigned) comparator->mask,
- (unsigned) comparator->function);
+ watchpoint->unique_id, dwt_num,
+ (unsigned) comparator->comp,
+ (unsigned) comparator->mask,
+ (unsigned) comparator->function);
return ERROR_OK;
}
-static int
-cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
+int cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct cortex_m3_dwt_comparator *comparator;
int dwt_num;
- if (!watchpoint->set)
- {
+ if (!watchpoint->set) {
LOG_WARNING("watchpoint (wpid: %d) not set",
- watchpoint->unique_id);
+ watchpoint->unique_id);
return ERROR_OK;
}
dwt_num = watchpoint->set - 1;
LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
- watchpoint->unique_id, dwt_num,
- (unsigned) watchpoint->address);
+ watchpoint->unique_id, dwt_num,
+ (unsigned) watchpoint->address);
- if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
- {
+ if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) {
LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
return ERROR_OK;
}
comparator->used = 0;
comparator->function = 0;
target_write_u32(target, comparator->dwt_comparator_address + 8,
- comparator->function);
+ comparator->function);
watchpoint->set = false;
return ERROR_OK;
}
-static int
-cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
+int cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- if (cortex_m3->dwt_comp_available < 1)
- {
+ if (cortex_m3->dwt_comp_available < 1) {
LOG_DEBUG("no comparators?");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
return ERROR_OK;
}
-static int
-cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
+int cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* REVISIT why check? DWT can be updated with core running ... */
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (watchpoint->set)
- {
cortex_m3_unset_watchpoint(target, watchpoint);
- }
cortex_m3->dwt_comp_available++;
LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
return ERROR_OK;
}
-static void cortex_m3_enable_watchpoints(struct target *target)
+void cortex_m3_enable_watchpoints(struct target *target)
{
struct watchpoint *watchpoint = target->watchpoints;
/* set any pending watchpoints */
- while (watchpoint)
- {
+ while (watchpoint) {
if (!watchpoint->set)
cortex_m3_set_watchpoint(target, watchpoint);
watchpoint = watchpoint->next;
}
static int cortex_m3_load_core_reg_u32(struct target *target,
- enum armv7m_regtype type, uint32_t num, uint32_t * value)
+ uint32_t num, uint32_t *value)
{
int retval;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.
*/
switch (num) {
- case 0 ... 18:
- /* read a normal core register */
- retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
+ case 0 ... 18:
+ /* read a normal core register */
+ retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
- if (retval != ERROR_OK)
- {
- LOG_ERROR("JTAG failure %i",retval);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
- break;
-
- case ARMV7M_PRIMASK:
- case ARMV7M_BASEPRI:
- case ARMV7M_FAULTMASK:
- case ARMV7M_CONTROL:
- /* Cortex-M3 packages these four registers as bitfields
- * in one Debug Core register. So say r0 and r2 docs;
- * it was removed from r1 docs, but still works.
- */
- cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("JTAG failure %i", retval);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
+ break;
- switch (num)
- {
- case ARMV7M_PRIMASK:
- *value = buf_get_u32((uint8_t*)value, 0, 1);
- break;
+ case ARMV7M_PRIMASK:
+ case ARMV7M_BASEPRI:
+ case ARMV7M_FAULTMASK:
+ case ARMV7M_CONTROL:
+ /* Cortex-M3 packages these four registers as bitfields
+ * in one Debug Core register. So say r0 and r2 docs;
+ * it was removed from r1 docs, but still works.
+ */
+ cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
- case ARMV7M_BASEPRI:
- *value = buf_get_u32((uint8_t*)value, 8, 8);
- break;
+ switch (num) {
+ case ARMV7M_PRIMASK:
+ *value = buf_get_u32((uint8_t *)value, 0, 1);
+ break;
- case ARMV7M_FAULTMASK:
- *value = buf_get_u32((uint8_t*)value, 16, 1);
- break;
+ case ARMV7M_BASEPRI:
+ *value = buf_get_u32((uint8_t *)value, 8, 8);
+ break;
- case ARMV7M_CONTROL:
- *value = buf_get_u32((uint8_t*)value, 24, 2);
- break;
- }
+ case ARMV7M_FAULTMASK:
+ *value = buf_get_u32((uint8_t *)value, 16, 1);
+ break;
- LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
- break;
+ case ARMV7M_CONTROL:
+ *value = buf_get_u32((uint8_t *)value, 24, 2);
+ break;
+ }
- default:
- return ERROR_INVALID_ARGUMENTS;
+ LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
+ break;
+
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
return ERROR_OK;
}
static int cortex_m3_store_core_reg_u32(struct target *target,
- enum armv7m_regtype type, uint32_t num, uint32_t value)
+ uint32_t num, uint32_t value)
{
int retval;
uint32_t reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
* Selector values for R0..R15, xPSR, MSP, and PSP.
*/
switch (num) {
- case 0 ... 18:
- retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
- if (retval != ERROR_OK)
- {
- struct reg *r;
+ case 0 ... 18:
+ retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
+ if (retval != ERROR_OK) {
+ struct reg *r;
+
+ LOG_ERROR("JTAG failure");
+ r = armv7m->arm.core_cache->reg_list + num;
+ r->dirty = r->valid;
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
+ break;
- LOG_ERROR("JTAG failure");
- r = armv7m->core_cache->reg_list + num;
- r->dirty = r->valid;
- return ERROR_JTAG_DEVICE_ERROR;
- }
- LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
- break;
-
- case ARMV7M_PRIMASK:
- case ARMV7M_BASEPRI:
- case ARMV7M_FAULTMASK:
- case ARMV7M_CONTROL:
- /* Cortex-M3 packages these four registers as bitfields
- * in one Debug Core register. So say r0 and r2 docs;
- * it was removed from r1 docs, but still works.
- */
- cortexm3_dap_read_coreregister_u32(swjdp, ®, 20);
+ case ARMV7M_PRIMASK:
+ case ARMV7M_BASEPRI:
+ case ARMV7M_FAULTMASK:
+ case ARMV7M_CONTROL:
+ /* Cortex-M3 packages these four registers as bitfields
+ * in one Debug Core register. So say r0 and r2 docs;
+ * it was removed from r1 docs, but still works.
+ */
+ cortexm3_dap_read_coreregister_u32(swjdp, ®, 20);
- switch (num)
- {
- case ARMV7M_PRIMASK:
- buf_set_u32((uint8_t*)®, 0, 1, value);
- break;
+ switch (num) {
+ case ARMV7M_PRIMASK:
+ buf_set_u32((uint8_t *)®, 0, 1, value);
+ break;
- case ARMV7M_BASEPRI:
- buf_set_u32((uint8_t*)®, 8, 8, value);
- break;
+ case ARMV7M_BASEPRI:
+ buf_set_u32((uint8_t *)®, 8, 8, value);
+ break;
- case ARMV7M_FAULTMASK:
- buf_set_u32((uint8_t*)®, 16, 1, value);
- break;
+ case ARMV7M_FAULTMASK:
+ buf_set_u32((uint8_t *)®, 16, 1, value);
+ break;
- case ARMV7M_CONTROL:
- buf_set_u32((uint8_t*)®, 24, 2, value);
- break;
- }
+ case ARMV7M_CONTROL:
+ buf_set_u32((uint8_t *)®, 24, 2, value);
+ break;
+ }
- cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
+ cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
- LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
- break;
+ LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
+ break;
- default:
- return ERROR_INVALID_ARGUMENTS;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
return ERROR_OK;
}
static int cortex_m3_read_memory(struct target *target, uint32_t address,
- uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
- int retval = ERROR_INVALID_ARGUMENTS;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (armv7m->arm.is_armv6m) {
+ /* armv6m does not handle unaligned memory access */
+ if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+ return ERROR_TARGET_UNALIGNED_ACCESS;
+ }
/* cortex_m3 handles unaligned memory access */
if (count && buffer) {
switch (size) {
- case 4:
- retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
- break;
- case 2:
- retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
- break;
- case 1:
- retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
- break;
+ case 4:
+ retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address, true);
+ break;
+ case 2:
+ retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
+ break;
+ case 1:
+ retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
+ break;
}
}
}
static int cortex_m3_write_memory(struct target *target, uint32_t address,
- uint32_t size, uint32_t count, const uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
- int retval = ERROR_INVALID_ARGUMENTS;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (armv7m->arm.is_armv6m) {
+ /* armv6m does not handle unaligned memory access */
+ if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+ return ERROR_TARGET_UNALIGNED_ACCESS;
+ }
if (count && buffer) {
switch (size) {
- case 4:
- retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
- break;
- case 2:
- retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
- break;
- case 1:
- retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
- break;
+ case 4:
+ retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address, true);
+ break;
+ case 2:
+ retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
+ break;
+ case 1:
+ retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
+ break;
}
}
return retval;
}
-static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
- uint32_t count, const uint8_t *buffer)
-{
- return cortex_m3_write_memory(target, address, 4, count, buffer);
-}
-
static int cortex_m3_init_target(struct command_context *cmd_ctx,
- struct target *target)
+ struct target *target)
{
armv7m_build_reg_cache(target);
return ERROR_OK;
*/
struct dwt_reg_state {
- struct target *target;
- uint32_t addr;
- uint32_t value; /* scratch/cache */
+ struct target *target;
+ uint32_t addr;
+ uint32_t value; /* scratch/cache */
};
static int cortex_m3_dwt_get_reg(struct reg *reg)
}
struct dwt_reg {
- uint32_t addr;
- char *name;
- unsigned size;
+ uint32_t addr;
+ char *name;
+ unsigned size;
};
static struct dwt_reg dwt_base_regs[] = {
.set = cortex_m3_dwt_set_reg,
};
-static void
-cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
+static void cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
{
struct dwt_reg_state *state;
r->type = &dwt_reg_type;
}
-static void
-cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
+void cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
{
uint32_t dwtcr;
struct reg_cache *cache;
for (reg = 0; reg < 2; reg++)
cortex_m3_dwt_addreg(target, cache->reg_list + reg,
- dwt_base_regs + reg);
+ dwt_base_regs + reg);
comparator = cm3->dwt_comparator_list;
for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
for (j = 0; j < 3; j++, reg++)
cortex_m3_dwt_addreg(target, cache->reg_list + reg,
- dwt_comp + 3 * i + j);
+ dwt_comp + 3 * i + j);
}
*register_get_last_cache_p(&target->reg_cache) = cache;
cm3->dwt_cache = cache;
LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
- dwtcr, cm3->dwt_num_comp,
- (dwtcr & (0xf << 24)) ? " only" : "/trigger");
+ dwtcr, cm3->dwt_num_comp,
+ (dwtcr & (0xf << 24)) ? " only" : "/trigger");
/* REVISIT: if num_comp > 1, check whether comparator #1 can
* implement single-address data value watchpoints ... so we
*/
}
-static int cortex_m3_examine(struct target *target)
+#define MVFR0 0xe000ef40
+#define MVFR1 0xe000ef44
+
+#define MVFR0_DEFAULT_M4 0x10110021
+#define MVFR1_DEFAULT_M4 0x11000011
+
+int cortex_m3_examine(struct target *target)
{
int retval;
- uint32_t cpuid, fpcr;
+ uint32_t cpuid, fpcr, mvfr0, mvfr1;
int i;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
- if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
- return retval;
+ /* stlink shares the examine handler but does not support
+ * all its calls */
+ if (!armv7m->stlink) {
+ retval = ahbap_debugport_init(swjdp);
+ if (retval != ERROR_OK)
+ return retval;
+ }
- if (!target_was_examined(target))
- {
+ if (!target_was_examined(target)) {
target_set_examined(target);
/* Read from Device Identification Registers */
if (retval != ERROR_OK)
return retval;
- if (((cpuid >> 4) & 0xc3f) == 0xc23)
- LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
- (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
+ /* Get CPU Type */
+ i = (cpuid >> 4) & 0xf;
+
+ LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
+ i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
+ /* test for floating point feature on cortex-m4 */
+ if (i == 4) {
+ target_read_u32(target, MVFR0, &mvfr0);
+ target_read_u32(target, MVFR1, &mvfr1);
+
+ if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
+ LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
+ armv7m->fp_feature = FPv4_SP;
+ }
+ } else if (i == 0) {
+ /* Cortex-M0 does not support unaligned memory access */
+ armv7m->arm.is_armv6m = true;
+ }
+
+ if (i == 4 || i == 3) {
+ /* Cortex-M3/M4 has 4096 bytes autoincrement range */
+ armv7m->dap.tar_autoincr_block = (1 << 12);
+ }
+
/* NOTE: FPB and DWT are both optional. */
/* Setup FPB */
target_read_u32(target, FP_CTRL, &fpcr);
cortex_m3->auto_bp_type = 1;
- cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
+ cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits
+ *[14:12]
+ *and [7:4]
+ **/
cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
cortex_m3->fp_code_available = cortex_m3->fp_num_code;
- cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
+ cortex_m3->fp_comparator_list = calloc(
+ cortex_m3->fp_num_code + cortex_m3->fp_num_lit,
+ sizeof(struct cortex_m3_fp_comparator));
cortex_m3->fpb_enabled = fpcr & 1;
- for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
- {
- cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
+ for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) {
+ cortex_m3->fp_comparator_list[i].type =
+ (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
}
- LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
+ LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
+ fpcr,
+ cortex_m3->fp_num_code,
+ cortex_m3->fp_num_lit);
/* Setup DWT */
cortex_m3_dwt_setup(cortex_m3, target);
/* These hardware breakpoints only work for code in flash! */
LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
- target_name(target),
- cortex_m3->fp_num_code,
- cortex_m3->dwt_num_comp);
+ target_name(target),
+ cortex_m3->fp_num_code,
+ cortex_m3->dwt_num_comp);
}
return ERROR_OK;
uint16_t dcrdr;
int retval;
- mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+ mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
*ctrl = (uint8_t)dcrdr;
*value = (uint8_t)(dcrdr >> 8);
/* write ack back to software dcc register
* signify we have read data */
- if (dcrdr & (1 << 0))
- {
+ if (dcrdr & (1 << 0)) {
dcrdr = 0;
- retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+ retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
if (retval != ERROR_OK)
return retval;
}
}
static int cortex_m3_target_request_data(struct target *target,
- uint32_t size, uint8_t *buffer)
+ uint32_t size, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
uint8_t data;
uint8_t ctrl;
uint32_t i;
- for (i = 0; i < (size * 4); i++)
- {
+ for (i = 0; i < (size * 4); i++) {
cortex_m3_dcc_read(swjdp, &data, &ctrl);
buffer[i] = data;
}
if (!target_was_examined(target))
return ERROR_OK;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
if (!target->dbg_msg_enabled)
return ERROR_OK;
- if (target->state == TARGET_RUNNING)
- {
+ if (target->state == TARGET_RUNNING) {
uint8_t data;
uint8_t ctrl;
cortex_m3_dcc_read(swjdp, &data, &ctrl);
/* check if we have data */
- if (ctrl & (1 << 0))
- {
+ if (ctrl & (1 << 0)) {
uint32_t request;
/* we assume target is quick enough */
}
static int cortex_m3_init_arch_info(struct target *target,
- struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
+ struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
{
int retval;
struct armv7m_common *armv7m = &cortex_m3->armv7m;
/* Leave (only) generic DAP stuff for debugport_init(); */
armv7m->dap.jtag_info = &cortex_m3->jtag_info;
armv7m->dap.memaccess_tck = 8;
- /* Cortex-M3 has 4096 bytes autoincrement range */
- armv7m->dap.tar_autoincr_block = (1 << 12);
+
+ /* Cortex-M3/M4 has 4096 bytes autoincrement range
+ * but set a safe default to 1024 to support Cortex-M0
+ * this will be changed in cortex_m3_examine if a M3/M4 is detected */
+ armv7m->dap.tar_autoincr_block = (1 << 10);
/* register arch-specific functions */
armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
- if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
- {
+ retval = arm_jtag_setup_connection(&cortex_m3->jtag_info);
+ if (retval != ERROR_OK)
return retval;
- }
return ERROR_OK;
}
static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
{
- struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
+ struct cortex_m3_common *cortex_m3 = calloc(1, sizeof(struct cortex_m3_common));
cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
cortex_m3_init_arch_info(target, cortex_m3, target->tap);
/*--------------------------------------------------------------------------*/
static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
- struct cortex_m3_common *cm3)
+ struct cortex_m3_common *cm3)
{
if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
command_print(cmd_ctx, "target is not a Cortex-M3");
char name[10];
unsigned mask;
} vec_ids[] = {
- { "hard_err", VC_HARDERR, },
- { "int_err", VC_INTERR, },
- { "bus_err", VC_BUSERR, },
- { "state_err", VC_STATERR, },
- { "chk_err", VC_CHKERR, },
- { "nocp_err", VC_NOCPERR, },
- { "mm_err", VC_MMERR, },
- { "reset", VC_CORERESET, },
+ { "hard_err", VC_HARDERR, },
+ { "int_err", VC_INTERR, },
+ { "bus_err", VC_BUSERR, },
+ { "state_err", VC_STATERR, },
+ { "chk_err", VC_CHKERR, },
+ { "nocp_err", VC_NOCPERR, },
+ { "mm_err", VC_MMERR, },
+ { "reset", VC_CORERESET, },
};
COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
struct target *target = get_current_target(CMD_CTX);
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
uint32_t demcr = 0;
int retval;
| VC_STATERR | VC_CHKERR | VC_NOCPERR
| VC_MMERR | VC_CORERESET;
goto write;
- } else if (strcmp(CMD_ARGV[0], "none") == 0) {
+ } else if (strcmp(CMD_ARGV[0], "none") == 0)
goto write;
- }
}
while (CMD_ARGC-- > 0) {
unsigned i;
}
if (i == ARRAY_SIZE(vec_ids)) {
LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
- return ERROR_INVALID_ARGUMENTS;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
}
write:
*/
}
- for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
- {
+ for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
(demcr & vec_ids[i].mask) ? "catch" : "ignore");
}
static const Jim_Nvp nvp_maskisr_modes[] = {
{ .name = "auto", .value = CORTEX_M3_ISRMASK_AUTO },
- { .name = "off" , .value = CORTEX_M3_ISRMASK_OFF },
- { .name = "on" , .value = CORTEX_M3_ISRMASK_ON },
- { .name = NULL , .value = -1 },
+ { .name = "off", .value = CORTEX_M3_ISRMASK_OFF },
+ { .name = "on", .value = CORTEX_M3_ISRMASK_ON },
+ { .name = NULL, .value = -1 },
};
const Jim_Nvp *n;
if (retval != ERROR_OK)
return retval;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
- if (CMD_ARGC > 0)
- {
+ if (CMD_ARGC > 0) {
n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
if (n->name == NULL)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
cortex_m3->isrmasking_mode = n->value;
- if(cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON)
- {
+ if (cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON)
cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
- }
else
- {
cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
- }
}
n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
if (retval != ERROR_OK)
return retval;
- if (CMD_ARGC > 0)
- {
+ if (CMD_ARGC > 0) {
if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
else if (strcmp(*CMD_ARGV, "vectreset") == 0)
cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
}
- switch (cortex_m3->soft_reset_config)
- {
+ switch (cortex_m3->soft_reset_config) {
case CORTEX_M3_RESET_SYSRESETREQ:
reset_config = "sysresetreq";
break;
.name = "cortex_m3",
.mode = COMMAND_EXEC,
.help = "Cortex-M3 command group",
+ .usage = "",
.chain = cortex_m3_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
-struct target_type cortexm3_target =
-{
+struct target_type cortexm3_target = {
.name = "cortex_m3",
.poll = cortex_m3_poll,
.read_memory = cortex_m3_read_memory,
.write_memory = cortex_m3_write_memory,
- .bulk_write_memory = cortex_m3_bulk_write_memory,
.checksum_memory = armv7m_checksum_memory,
.blank_check_memory = armv7m_blank_check_memory,
Code Review / openocd.git / blobdiff