target: disable armv6m unaligned memory access

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 625065c57957e876e9eecb8227b564b8f9771555..e4374318aa1afb71a42a97f18cd60c8d356cde8f 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -31,6 +31,7 @@
 #include "config.h"
 #endif
 
+#include "jtag/interface.h"
 #include "breakpoints.h"
 #include "cortex_m.h"
 #include "target_request.h"
@@ -609,7 +610,7 @@ static int cortex_m3_halt(struct target *target)
                        return ERROR_TARGET_FAILURE;
                } else {
                        /* we came here in a reset_halt or reset_init sequence
-                        * debug entry was already prepared in cortex_m3_prepare_reset_halt()
+                        * debug entry was already prepared in cortex_m3_assert_reset()
                         */
                        target->debug_reason = DBG_REASON_DBGRQ;
 
@@ -951,6 +952,16 @@ static int cortex_m3_assert_reset(struct target *target)
                return ERROR_OK;
        }
 
+       /* some cores support connecting while srst is asserted
+        * use that mode is it has been configured */
+
+       bool srst_asserted = false;
+
+       if (jtag_reset_config & RESET_SRST_NO_GATING) {
+               adapter_assert_reset();
+               srst_asserted = true;
+       }
+
        /* Enable debug requests */
        int retval;
        retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -995,10 +1006,8 @@ static int cortex_m3_assert_reset(struct target *target)
 
        if (jtag_reset_config & RESET_HAS_SRST) {
                /* default to asserting srst */
-               if (jtag_reset_config & RESET_SRST_PULLS_TRST)
-                       jtag_add_reset(1, 1);
-               else
-                       jtag_add_reset(0, 1);
+               if (!srst_asserted)
+                       adapter_assert_reset();
        } else {
                /* Use a standard Cortex-M3 software reset mechanism.
                 * We default to using VECRESET as it is supported on all current cores.
@@ -1051,7 +1060,7 @@ static int cortex_m3_deassert_reset(struct target *target)
                target_state_name(target));
 
        /* deassert reset lines */
-       jtag_add_reset(0, 0);
+       adapter_deassert_reset();
 
        return ERROR_OK;
 }
@@ -1561,6 +1570,12 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
        struct adiv5_dap *swjdp = &armv7m->dap;
        int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
+       if (armv7m->arm.is_armv6m) {
+               /* armv6m does not handle unaligned memory access */
+               if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+                       return ERROR_TARGET_UNALIGNED_ACCESS;
+       }
+
        /* cortex_m3 handles unaligned memory access */
        if (count && buffer) {
                switch (size) {
@@ -1586,6 +1601,12 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
        struct adiv5_dap *swjdp = &armv7m->dap;
        int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
+       if (armv7m->arm.is_armv6m) {
+               /* armv6m does not handle unaligned memory access */
+               if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+                       return ERROR_TARGET_UNALIGNED_ACCESS;
+       }
+
        if (count && buffer) {
                switch (size) {
                        case 4:
@@ -1756,17 +1777,28 @@ fail1:
         */
 }
 
-static int cortex_m3_examine(struct target *target)
+#define MVFR0 0xe000ef40
+#define MVFR1 0xe000ef44
+
+#define MVFR0_DEFAULT_M4 0x10110021
+#define MVFR1_DEFAULT_M4 0x11000011
+
+int cortex_m3_examine(struct target *target)
 {
        int retval;
-       uint32_t cpuid, fpcr;
+       uint32_t cpuid, fpcr, mvfr0, mvfr1;
        int i;
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+       struct armv7m_common *armv7m = target_to_armv7m(target);
 
-       retval = ahbap_debugport_init(swjdp);
-       if (retval != ERROR_OK)
-               return retval;
+       /* stlink shares the examine handler but does not support
+        * all its calls */
+       if (!armv7m->stlink) {
+               retval = ahbap_debugport_init(swjdp);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
 
        if (!target_was_examined(target)) {
                target_set_examined(target);
@@ -1776,11 +1808,27 @@ static int cortex_m3_examine(struct target *target)
                if (retval != ERROR_OK)
                        return retval;
 
-               if (((cpuid >> 4) & 0xc3f) == 0xc23)
-                       LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
-                               (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
+               /* Get CPU Type */
+               i = (cpuid >> 4) & 0xf;
+
+               LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
+                               i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
                LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
+               /* test for floating point feature on cortex-m4 */
+               if (i == 4) {
+                       target_read_u32(target, MVFR0, &mvfr0);
+                       target_read_u32(target, MVFR1, &mvfr1);
+
+                       if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
+                               LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
+                               armv7m->fp_feature = FPv4_SP;
+                       }
+               } else if (i == 0) {
+                       /* Cortex-M0 does not support unaligned memory access */
+                       armv7m->arm.is_armv6m = true;
+               }
+
                /* NOTE: FPB and DWT are both optional. */
 
                /* Setup FPB */