TRST is asserted *before* target->type->assert_reset() is invoked. Removed old code.

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 653ebab09782423d2ccc1128bf622e9a973c61c3..6bdb1df67b4c4b899e5df0989bf39a04ecf088f3 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -691,14 +691,6 @@ int cortex_m3_assert_reset(target_t *target)
                ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
        }
        
-       if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
-       {
-               /* assert SRST and TRST */
-               /* system would get ouf sync if we didn't reset test-logic, too */
-               jtag_add_reset(1, 1);
-               jtag_add_sleep(5000);
-       }
-
        if (jtag_reset_config & RESET_SRST_PULLS_TRST)
        {
                jtag_add_reset(1, 1);
@@ -1336,6 +1328,8 @@ int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer)
 int cortex_m3_handle_target_request(void *priv)
 {
        target_t *target = priv;
+       if (!target->type->examined)
+               return ERROR_OK;
        armv7m_common_t *armv7m = target->arch_info;
        cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
        swjdp_common_t *swjdp = &cortex_m3->swjdp_info;