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target: create/use register_cache_invalidate()
[openocd.git] / src / target / cortex_m3.c
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 35ca5a5c125f4359872dc27053725020db30c135..8279a8b939400270960a6dbbaf5b25d01a190934 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -36,14 +36,13 @@
 #include "target_request.h"
 #include "target_type.h"
 #include "arm_disassembler.h"
+#include "register.h"
 
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  */
 
-#define ARRAY_SIZE(x)  ((int)(sizeof(x)/sizeof((x)[0])))
-
 
 /* forward declarations */
 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
@@ -222,7 +221,7 @@ static int cortex_m3_endreset_event(struct target *target)
        }
        swjdp_transaction_endcheck(swjdp);
 
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
        /* make sure we have latest dhcsr flags */
        mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -335,6 +334,9 @@ static int cortex_m3_debug_entry(struct target *target)
        xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
 
 #ifdef ARMV7_GDB_HACKS
+       /* FIXME this breaks on scan chains with more than one Cortex-M3.
+        * Instead, each CM3 should have its own dummy value...
+        */
        /* copy real xpsr reg for gdb, setting thumb bit */
        buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
        buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
@@ -508,7 +510,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
        target->state = TARGET_RESET;
 
        /* registers are now invalid */
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
        while (timeout < 100)
        {
@@ -615,7 +617,8 @@ static int cortex_m3_resume(struct target *target, int current,
        target->debug_reason = DBG_REASON_NOTHALTED;
 
        /* registers are now invalid */
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(armv7m->core_cache);
+
        if (!debug_execution)
        {
                target->state = TARGET_RUNNING;
@@ -671,7 +674,7 @@ static int cortex_m3_step(struct target *target, int current,
        mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 
        /* registers are now invalid */
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
        if (breakpoint)
                cortex_m3_set_breakpoint(target, breakpoint);
@@ -810,7 +813,7 @@ static int cortex_m3_assert_reset(struct target *target)
        target->state = TARGET_RESET;
        jtag_add_sleep(50000);
 
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
        if (target->reset_halt)
        {
@@ -859,9 +862,8 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
                        fp_num++;
                if (fp_num >= cortex_m3->fp_num_code)
                {
-                       LOG_DEBUG("ERROR Can not find free FP Comparator");
-                       LOG_WARNING("ERROR Can not find free FP Comparator");
-                       exit(-1);
+                       LOG_ERROR("Can not find free FPB Comparator!");
+                       return ERROR_FAIL;
                }
                breakpoint->set = fp_num + 1;
                hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
@@ -1373,16 +1375,11 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct swjdp_common *swjdp = &armv7m->swjdp_info;
-       int retval;
-
-       /* sanitize arguments */
-       if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-               return ERROR_INVALID_ARGUMENTS;
+       int retval = ERROR_INVALID_ARGUMENTS;
 
        /* cortex_m3 handles unaligned memory access */
-
-       switch (size)
-       {
+       if (count && buffer) {
+               switch (size) {
                case 4:
                        retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
                        break;
@@ -1392,9 +1389,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
                case 1:
                        retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
+               }
        }
 
        return retval;
@@ -1405,14 +1400,10 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct swjdp_common *swjdp = &armv7m->swjdp_info;
-       int retval;
+       int retval = ERROR_INVALID_ARGUMENTS;
 
-       /* sanitize arguments */
-       if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-               return ERROR_INVALID_ARGUMENTS;
-
-       switch (size)
-       {
+       if (count && buffer) {
+               switch (size) {
                case 4:
                        retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
                        break;
@@ -1422,9 +1413,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
                case 1:
                        retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
+               }
        }
 
        return retval;
@@ -1493,7 +1482,10 @@ static struct dwt_reg dwt_comp[] = {
 #undef DWT_COMPARATOR
 };
 
-static int dwt_reg_type = -1;
+static const struct reg_arch_type dwt_reg_type = {
+       .get = cortex_m3_dwt_get_reg,
+       .set = cortex_m3_dwt_set_reg,
+};
 
 static void
 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
@@ -1510,7 +1502,7 @@ cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
        r->size = d->size;
        r->value = &state->value;
        r->arch_info = state;
-       r->arch_type = dwt_reg_type;
+       r->type = &dwt_reg_type;
 }
 
 static void
@@ -1527,10 +1519,6 @@ cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
                return;
        }
 
-       if (dwt_reg_type < 0)
-               dwt_reg_type = register_reg_arch_type(cortex_m3_dwt_get_reg,
-                               cortex_m3_dwt_set_reg);
-
        cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
        cm3->dwt_comp_available = cm3->dwt_num_comp;
        cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
@@ -1785,26 +1773,26 @@ static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
 {
        int retval;
-       struct target *target = get_current_target(cmd_ctx);
+       struct target *target = get_current_target(CMD_CTX);
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        uint32_t address;
        unsigned long count = 1;
        struct arm_instruction cur_instruction;
 
-       retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
+       retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
        if (retval != ERROR_OK)
                return retval;
 
        errno = 0;
-       switch (argc) {
+       switch (CMD_ARGC) {
        case 2:
-               COMMAND_PARSE_NUMBER(ulong, args[1], count);
+               COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
                /* FALL THROUGH */
        case 1:
-               COMMAND_PARSE_NUMBER(u32, args[0], address);
+               COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
                break;
        default:
-               command_print(cmd_ctx,
+               command_print(CMD_CTX,
                        "usage: cortex_m3 disassemble <address> [<count>]");
                return ERROR_OK;
        }
@@ -1813,7 +1801,7 @@ COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
                retval = thumb2_opcode(target, address, &cur_instruction);
                if (retval != ERROR_OK)
                        return retval;
-               command_print(cmd_ctx, "%s", cur_instruction.text);
+               command_print(CMD_CTX, "%s", cur_instruction.text);
                address += cur_instruction.instruction_size;
        }
 
@@ -1836,42 +1824,42 @@ static const struct {
 
 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
 {
-       struct target *target = get_current_target(cmd_ctx);
+       struct target *target = get_current_target(CMD_CTX);
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        struct armv7m_common *armv7m = &cortex_m3->armv7m;
        struct swjdp_common *swjdp = &armv7m->swjdp_info;
        uint32_t demcr = 0;
        int retval;
-       int i;
 
-       retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
+       retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
        if (retval != ERROR_OK)
                return retval;
 
        mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
 
-       if (argc > 0) {
+       if (CMD_ARGC > 0) {
                unsigned catch = 0;
 
-               if (argc == 1) {
-                       if (strcmp(args[0], "all") == 0) {
+               if (CMD_ARGC == 1) {
+                       if (strcmp(CMD_ARGV[0], "all") == 0) {
                                catch = VC_HARDERR | VC_INTERR | VC_BUSERR
                                        | VC_STATERR | VC_CHKERR | VC_NOCPERR
                                        | VC_MMERR | VC_CORERESET;
                                goto write;
-                       } else if (strcmp(args[0], "none") == 0) {
+                       } else if (strcmp(CMD_ARGV[0], "none") == 0) {
                                goto write;
                        }
                }
-               while (argc-- > 0) {
+               while (CMD_ARGC-- > 0) {
+                       unsigned i;
                        for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
-                               if (strcmp(args[argc], vec_ids[i].name) != 0)
+                               if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
                                        continue;
                                catch |= vec_ids[i].mask;
                                break;
                        }
                        if (i == ARRAY_SIZE(vec_ids)) {
-                               LOG_ERROR("No CM3 vector '%s'", args[argc]);
+                               LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
                                return ERROR_INVALID_ARGUMENTS;
                        }
                }
@@ -1884,46 +1872,41 @@ write:
                mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
        }
 
-       for (i = 0; i < ARRAY_SIZE(vec_ids); i++)
-               command_print(cmd_ctx, "%9s: %s", vec_ids[i].name,
+       for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
+       {
+               command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
                        (demcr & vec_ids[i].mask) ? "catch" : "ignore");
+       }
 
        return ERROR_OK;
 }
 
 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
 {
-       struct target *target = get_current_target(cmd_ctx);
+       struct target *target = get_current_target(CMD_CTX);
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        int retval;
 
-       retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
+       retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
        if (retval != ERROR_OK)
                return retval;
 
        if (target->state != TARGET_HALTED)
        {
-               command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
+               command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
                return ERROR_OK;
        }
 
-       if (argc > 0)
+       if (CMD_ARGC > 0)
        {
-               if (!strcmp(args[0], "on"))
-               {
-                       cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
-               }
-               else if (!strcmp(args[0], "off"))
-               {
-                       cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
-               }
-               else
-               {
-                       command_print(cmd_ctx, "usage: cortex_m3 maskisr ['on'|'off']");
-               }
+               bool enable;
+               COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
+               uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
+               uint32_t mask_off = enable ? 0 : C_MASKINTS;
+               cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
        }
 
-       command_print(cmd_ctx, "cortex_m3 interrupt mask %s",
+       command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
                        (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
 
        return ERROR_OK;
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