target: create/use register_cache_invalidate()

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index c9938c9c422154335e61a32e71256141aee9aef3..8279a8b939400270960a6dbbaf5b25d01a190934 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -221,7 +221,7 @@ static int cortex_m3_endreset_event(struct target *target)
        }
        swjdp_transaction_endcheck(swjdp);
 
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
        /* make sure we have latest dhcsr flags */
        mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -334,6 +334,9 @@ static int cortex_m3_debug_entry(struct target *target)
        xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
 
 #ifdef ARMV7_GDB_HACKS
+       /* FIXME this breaks on scan chains with more than one Cortex-M3.
+        * Instead, each CM3 should have its own dummy value...
+        */
        /* copy real xpsr reg for gdb, setting thumb bit */
        buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
        buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
@@ -507,7 +510,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
        target->state = TARGET_RESET;
 
        /* registers are now invalid */
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
        while (timeout < 100)
        {
@@ -614,7 +617,8 @@ static int cortex_m3_resume(struct target *target, int current,
        target->debug_reason = DBG_REASON_NOTHALTED;
 
        /* registers are now invalid */
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(armv7m->core_cache);
+
        if (!debug_execution)
        {
                target->state = TARGET_RUNNING;
@@ -670,7 +674,7 @@ static int cortex_m3_step(struct target *target, int current,
        mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 
        /* registers are now invalid */
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
        if (breakpoint)
                cortex_m3_set_breakpoint(target, breakpoint);
@@ -809,7 +813,7 @@ static int cortex_m3_assert_reset(struct target *target)
        target->state = TARGET_RESET;
        jtag_add_sleep(50000);
 
-       armv7m_invalidate_core_regs(target);
+       register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
        if (target->reset_halt)
        {
@@ -1895,18 +1899,11 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
 
        if (CMD_ARGC > 0)
        {
-               if (!strcmp(CMD_ARGV[0], "on"))
-               {
-                       cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
-               }
-               else if (!strcmp(CMD_ARGV[0], "off"))
-               {
-                       cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
-               }
-               else
-               {
-                       command_print(CMD_CTX, "usage: cortex_m3 maskisr ['on'|'off']");
-               }
+               bool enable;
+               COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
+               uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
+               uint32_t mask_off = enable ? 0 : C_MASKINTS;
+               cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
        }
 
        command_print(CMD_CTX, "cortex_m3 interrupt mask %s",