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oocd_trace_t -> struct oocd_trace
[openocd.git] / src / target / cortex_m3.c
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 6b015ca0f5e268660b9b2ed63b623dc06215f45e..9d2c54f732e3fee0616ba666612a475ca861e974 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -56,13 +56,7 @@ extern uint8_t armv7m_gdb_dummy_cpsr_value[];
 extern reg_t armv7m_gdb_dummy_cpsr_reg;
 #endif
 
-static int cortex_m3_has_mmu(struct target_s *target, bool *has_mmu)
-{
-       *has_mmu = false;
-       return ERROR_OK;
-}
-
-static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
+static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
                uint32_t *value, int regnum)
 {
        int retval;
@@ -93,7 +87,7 @@ static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
        return retval;
 }
 
-static int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp,
+static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
                uint32_t value, int regnum)
 {
        int retval;
@@ -127,8 +121,8 @@ static int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp,
 static int cortex_m3_write_debug_halt_mask(target_t *target,
                uint32_t mask_on, uint32_t mask_off)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 
        /* mask off status bits */
        cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
@@ -140,8 +134,8 @@ static int cortex_m3_write_debug_halt_mask(target_t *target,
 
 static int cortex_m3_clear_halt(target_t *target)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 
        /* clear step if any */
        cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
@@ -157,8 +151,8 @@ static int cortex_m3_clear_halt(target_t *target)
 
 static int cortex_m3_single_step_core(target_t *target)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
        uint32_t dhcsr_save;
 
        /* backup dhcsr reg */
@@ -181,8 +175,8 @@ static int cortex_m3_endreset_event(target_t *target)
 {
        int i;
        uint32_t dcb_demcr;
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
        cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
        cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
 
@@ -237,7 +231,7 @@ static int cortex_m3_endreset_event(target_t *target)
 
 static int cortex_m3_examine_debug_reason(target_t *target)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 
        /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
        /* only check the debug reason if we don't know it already */
@@ -265,8 +259,8 @@ static int cortex_m3_examine_debug_reason(target_t *target)
 static int cortex_m3_examine_exception_reason(target_t *target)
 {
        uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
-       struct armv7m_common_s *armv7m = target_to_armv7m(target);
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct armv7m_common *armv7m = target_to_armv7m(target);
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
        mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
        switch (armv7m->exception_number)
@@ -315,9 +309,9 @@ static int cortex_m3_debug_entry(target_t *target)
        int i;
        uint32_t xPSR;
        int retval;
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct armv7m_common *armv7m = &cortex_m3->armv7m;
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
        LOG_DEBUG(" ");
 
@@ -386,8 +380,8 @@ static int cortex_m3_poll(target_t *target)
 {
        int retval;
        enum target_state prev_target_state = target->state;
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 
        /* Read from Debug Halting Control and Status Register */
        retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -500,8 +494,8 @@ static int cortex_m3_halt(target_t *target)
 
 static int cortex_m3_soft_reset_halt(struct target_s *target)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
        uint32_t dcb_dhcsr = 0;
        int retval, timeout = 0;
 
@@ -553,7 +547,7 @@ static void cortex_m3_enable_breakpoints(struct target_s *target)
 static int cortex_m3_resume(struct target_s *target, int current,
                uint32_t address, int handle_breakpoints, int debug_execution)
 {
-       struct armv7m_common_s *armv7m = target_to_armv7m(target);
+       struct armv7m_common *armv7m = target_to_armv7m(target);
        breakpoint_t *breakpoint = NULL;
        uint32_t resume_pc;
 
@@ -641,9 +635,9 @@ static int cortex_m3_resume(struct target_s *target, int current,
 static int cortex_m3_step(struct target_s *target, int current,
                uint32_t address, int handle_breakpoints)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct armv7m_common *armv7m = &cortex_m3->armv7m;
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
        breakpoint_t *breakpoint = NULL;
 
        if (target->state != TARGET_HALTED)
@@ -692,8 +686,8 @@ static int cortex_m3_step(struct target_s *target, int current,
 
 static int cortex_m3_assert_reset(target_t *target)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
        int assert_srst = 1;
 
        LOG_DEBUG("target->state: %s",
@@ -844,7 +838,7 @@ cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        int retval;
        int fp_num = 0;
        uint32_t hilo;
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        cortex_m3_fp_comparator_t *comparator_list = cortex_m3->fp_comparator_list;
 
        if (breakpoint->set)
@@ -909,7 +903,7 @@ static int
 cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
        int retval;
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
 
        if (!breakpoint->set)
@@ -963,7 +957,7 @@ cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 static int
 cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 
        if (cortex_m3->auto_bp_type)
        {
@@ -1012,7 +1006,7 @@ cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 static int
 cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 
        /* REVISIT why check? FBP can be updated with core running ... */
        if (target->state != TARGET_HALTED)
@@ -1038,11 +1032,11 @@ cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 }
 
 static int
-cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
 {
        int dwt_num = 0;
        uint32_t mask, temp;
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 
        /* watchpoint params were validated earlier */
        mask = 0;
@@ -1103,9 +1097,9 @@ cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 }
 
 static int
-cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        cortex_m3_dwt_comparator_t *comparator;
        int dwt_num;
 
@@ -1140,9 +1134,9 @@ cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 }
 
 static int
-cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 
        /* REVISIT why check? DWT can be updated with core running ... */
        if (target->state != TARGET_HALTED)
@@ -1198,9 +1192,9 @@ cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 }
 
 static int
-cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
 {
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 
        /* REVISIT why check? DWT can be updated with core running ... */
        if (target->state != TARGET_HALTED)
@@ -1222,7 +1216,7 @@ cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 
 static void cortex_m3_enable_watchpoints(struct target_s *target)
 {
-       watchpoint_t *watchpoint = target->watchpoints;
+       struct watchpoint *watchpoint = target->watchpoints;
 
        /* set any pending watchpoints */
        while (watchpoint)
@@ -1237,8 +1231,8 @@ static int cortex_m3_load_core_reg_u32(struct target_s *target,
                enum armv7m_regtype type, uint32_t num, uint32_t * value)
 {
        int retval;
-       struct armv7m_common_s *armv7m = target_to_armv7m(target);
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct armv7m_common *armv7m = target_to_armv7m(target);
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
        /* NOTE:  we "know" here that the register identifiers used
         * in the v7m header match the Cortex-M3 Debug Core Register
@@ -1301,8 +1295,8 @@ static int cortex_m3_store_core_reg_u32(struct target_s *target,
 {
        int retval;
        uint32_t reg;
-       struct armv7m_common_s *armv7m = target_to_armv7m(target);
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct armv7m_common *armv7m = target_to_armv7m(target);
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
 #ifdef ARMV7_GDB_HACKS
        /* If the LR register is being modified, make sure it will put us
@@ -1376,8 +1370,8 @@ static int cortex_m3_store_core_reg_u32(struct target_s *target,
 static int cortex_m3_read_memory(struct target_s *target, uint32_t address,
                uint32_t size, uint32_t count, uint8_t *buffer)
 {
-       struct armv7m_common_s *armv7m = target_to_armv7m(target);
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct armv7m_common *armv7m = target_to_armv7m(target);
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
        int retval;
 
        /* sanitize arguments */
@@ -1408,8 +1402,8 @@ static int cortex_m3_read_memory(struct target_s *target, uint32_t address,
 static int cortex_m3_write_memory(struct target_s *target, uint32_t address,
                uint32_t size, uint32_t count, uint8_t *buffer)
 {
-       struct armv7m_common_s *armv7m = target_to_armv7m(target);
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct armv7m_common *armv7m = target_to_armv7m(target);
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
        int retval;
 
        /* sanitize arguments */
@@ -1519,7 +1513,7 @@ cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d)
 }
 
 static void
-cortex_m3_dwt_setup(cortex_m3_common_t *cm3, struct target_s *target)
+cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target_s *target)
 {
        uint32_t dwtcr;
        struct reg_cache_s *cache;
@@ -1593,8 +1587,8 @@ static int cortex_m3_examine(struct target_s *target)
        int retval;
        uint32_t cpuid, fpcr;
        int i;
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 
        if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
                return retval;
@@ -1636,7 +1630,7 @@ static int cortex_m3_examine(struct target_s *target)
        return ERROR_OK;
 }
 
-static int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
 {
        uint16_t dcrdr;
 
@@ -1660,8 +1654,8 @@ static int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ct
 static int cortex_m3_target_request_data(target_t *target,
                uint32_t size, uint8_t *buffer)
 {
-       struct armv7m_common_s *armv7m = target_to_armv7m(target);
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct armv7m_common *armv7m = target_to_armv7m(target);
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
        uint8_t data;
        uint8_t ctrl;
        uint32_t i;
@@ -1680,8 +1674,8 @@ static int cortex_m3_handle_target_request(void *priv)
        target_t *target = priv;
        if (!target_was_examined(target))
                return ERROR_OK;
-       struct armv7m_common_s *armv7m = target_to_armv7m(target);
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct armv7m_common *armv7m = target_to_armv7m(target);
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
        if (!target->dbg_msg_enabled)
                return ERROR_OK;
@@ -1714,10 +1708,10 @@ static int cortex_m3_handle_target_request(void *priv)
 }
 
 static int cortex_m3_init_arch_info(target_t *target,
-               cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
+               struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
 {
        int retval;
-       struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
+       struct armv7m_common *armv7m = &cortex_m3->armv7m;
 
        armv7m_init_arch_info(target, armv7m);
 
@@ -1755,7 +1749,7 @@ static int cortex_m3_init_arch_info(target_t *target,
 
 static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
 {
-       cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
+       struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
 
        cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
        cortex_m3_init_arch_info(target, cortex_m3, target->tap);
@@ -1766,7 +1760,7 @@ static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
 /*--------------------------------------------------------------------------*/
 
 static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx,
-               struct cortex_m3_common_s *cm3)
+               struct cortex_m3_common *cm3)
 {
        if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
                command_print(cmd_ctx, "target is not a Cortex-M3");
@@ -1787,13 +1781,11 @@ static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx,
  * that *only* Thumb2 disassembly matters.  There are also some small
  * additions to Thumb2 that are specific to ARMv7-M.
  */
-static int
-handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx,
-               char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
 {
        int retval;
        target_t *target = get_current_target(cmd_ctx);
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        uint32_t address;
        unsigned long count = 1;
        arm_instruction_t cur_instruction;
@@ -1841,14 +1833,12 @@ static const struct {
        { "reset",      VC_CORERESET, },
 };
 
-static int
-handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx,
-               char *cmd, char **argv, int argc)
+COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
 {
        target_t *target = get_current_target(cmd_ctx);
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
-       struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
-       swjdp_common_t *swjdp = &armv7m->swjdp_info;
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+       struct armv7m_common *armv7m = &cortex_m3->armv7m;
+       struct swjdp_common *swjdp = &armv7m->swjdp_info;
        uint32_t demcr = 0;
        int retval;
        int i;
@@ -1863,24 +1853,24 @@ handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx,
                unsigned catch = 0;
 
                if (argc == 1) {
-                       if (strcmp(argv[0], "all") == 0) {
+                       if (strcmp(args[0], "all") == 0) {
                                catch = VC_HARDERR | VC_INTERR | VC_BUSERR
                                        | VC_STATERR | VC_CHKERR | VC_NOCPERR
                                        | VC_MMERR | VC_CORERESET;
                                goto write;
-                       } else if (strcmp(argv[0], "none") == 0) {
+                       } else if (strcmp(args[0], "none") == 0) {
                                goto write;
                        }
                }
                while (argc-- > 0) {
                        for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
-                               if (strcmp(argv[argc], vec_ids[i].name) != 0)
+                               if (strcmp(args[argc], vec_ids[i].name) != 0)
                                        continue;
                                catch |= vec_ids[i].mask;
                                break;
                        }
                        if (i == ARRAY_SIZE(vec_ids)) {
-                               LOG_ERROR("No CM3 vector '%s'", argv[argc]);
+                               LOG_ERROR("No CM3 vector '%s'", args[argc]);
                                return ERROR_INVALID_ARGUMENTS;
                        }
                }
@@ -1900,12 +1890,10 @@ write:
        return ERROR_OK;
 }
 
-static int
-handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx,
-               char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
 {
        target_t *target = get_current_target(cmd_ctx);
-       struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+       struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        int retval;
 
        retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
@@ -1914,7 +1902,7 @@ handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx,
 
        if (target->state != TARGET_HALTED)
        {
-               command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
+               command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
                return ERROR_OK;
        }
 
@@ -1998,6 +1986,5 @@ target_type_t cortexm3_target =
        .register_commands = cortex_m3_register_commands,
        .target_create = cortex_m3_target_create,
        .init_target = cortex_m3_init_target,
-       .has_mmu = cortex_m3_has_mmu,
        .examine = cortex_m3_examine,
 };
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