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Remove whitespace that occurs before ')'.
[openocd.git] / src / target / cortex_m3.c
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 644f68161f9bab4ce0cef33a170e0f874a493113..b913c4ee178600451c10fafd7d0ecef5a856c6fb 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -109,11 +109,11 @@ int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, i
 
        /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
-       dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum );
+       dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
 
        /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
-       dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+       dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 
        mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
        retval = swjdp_transaction_endcheck(swjdp);
@@ -134,11 +134,11 @@ int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, i
 
        /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
-       dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+       dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 
-       /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR     ); */
+       /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
-       dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
+       dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 
        mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
        retval = swjdp_transaction_endcheck(swjdp);
@@ -204,7 +204,7 @@ int cortex_m3_single_step_core(target_t *target)
        return ERROR_OK;
 }
 
-int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */ )
+int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */)
 {
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -444,7 +444,7 @@ int cortex_m3_debug_entry(target_t *target)
        LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
                armv7m_mode_strings[armv7m->core_mode],
                *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
-               Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+               Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
 
        if (armv7m->post_debug_entry)
                armv7m->post_debug_entry(target);
@@ -520,7 +520,7 @@ int cortex_m3_poll(target_t *target)
 #if 0
        /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script  */
        mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
-       LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+       LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
 #endif
 
        return ERROR_OK;
@@ -529,7 +529,7 @@ int cortex_m3_poll(target_t *target)
 int cortex_m3_halt(target_t *target)
 {
        LOG_DEBUG("target->state: %s",
-               Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
+               Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
 
        if (target->state == TARGET_HALTED)
        {
@@ -641,7 +641,7 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int
 
                /* Make sure we are in Thumb mode */
                buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
-                       buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24));
+                       buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
                armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
                armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
        }
@@ -694,7 +694,7 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int
        return ERROR_OK;
 }
 
-/* int irqstepcount=0; */
+/* int irqstepcount = 0; */
 int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
 {
        /* get pointers to arch-specific information */
@@ -751,7 +751,7 @@ int cortex_m3_assert_reset(target_t *target)
        int assert_srst = 1;
 
        LOG_DEBUG("target->state: %s",
-               Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+               Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();
        if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -765,7 +765,7 @@ int cortex_m3_assert_reset(target_t *target)
        if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
                mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 
-       mem_ap_write_u32(swjdp, DCB_DCRDR, 0 );
+       mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 
        if (!target->reset_halt)
        {
@@ -862,7 +862,7 @@ int cortex_m3_assert_reset(target_t *target)
 int cortex_m3_deassert_reset(target_t *target)
 {
        LOG_DEBUG("target->state: %s",
-               Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
+               Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
 
        /* deassert reset lines */
        jtag_add_reset(0, 0);
@@ -886,7 +886,7 @@ void cortex_m3_enable_breakpoints(struct target_s *target)
 int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
        int retval;
-       int fp_num=0;
+       int fp_num = 0;
        uint32_t hilo;
 
        /* get pointers to arch-specific information */
@@ -1075,7 +1075,7 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin
 
 int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
-       int dwt_num=0;
+       int dwt_num = 0;
        uint32_t mask, temp;
 
        /* get pointers to arch-specific information */
@@ -1112,8 +1112,8 @@ int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                comparator_list[dwt_num].mask = mask;
                comparator_list[dwt_num].function = watchpoint->rw + 5;
                target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp);
-               target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x4, comparator_list[dwt_num].mask);
-               target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
+               target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x4, comparator_list[dwt_num].mask);
+               target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function);
                LOG_DEBUG("dwt_num %i 0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 "", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
        }
        else
@@ -1149,7 +1149,7 @@ int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint
        }
        comparator_list[dwt_num].used = 0;
        comparator_list[dwt_num].function = 0;
-       target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
+       target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function);
 
        watchpoint->set = 0;
 
@@ -1285,7 +1285,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
         * in "thumb" mode, or an INVSTATE exception will occur. This is a
         * hack to deal with the fact that gdb will sometimes "forge"
         * return addresses, and doesn't set the LSB correctly (i.e., when
-        * printing expressions containing function calls, it sets LR=0.) */
+        * printing expressions containing function calls, it sets LR = 0.) */
 
        if (num == 14)
                value |= 0x01;
@@ -1491,7 +1491,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
 {
        uint16_t dcrdr;
 
-       mem_ap_read_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+       mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
        *ctrl = (uint8_t)dcrdr;
        *value = (uint8_t)(dcrdr >> 8);
 
@@ -1502,7 +1502,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
        if (dcrdr & (1 << 0))
        {
                dcrdr = 0;
-               mem_ap_write_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+               mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
        }
 
        return ERROR_OK;
@@ -1580,7 +1580,7 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
        armv7m->swjdp_info.ap_tar_value = -1;
        armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
        armv7m->swjdp_info.memaccess_tck = 8;
-       armv7m->swjdp_info.tar_autoincr_block = (1<<12);        /* Cortex-M3 has 4096 bytes autoincrement range */
+       armv7m->swjdp_info.tar_autoincr_block = (1 << 12);      /* Cortex-M3 has 4096 bytes autoincrement range */
 
        /* initialize arch-specific breakpoint handling */
 
@@ -1648,7 +1648,7 @@ int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx,
        {
                if (!strcmp(args[0], "on"))
                {
-                       cortex_m3_write_debug_halt_mask(target, C_HALT|C_MASKINTS, 0);
+                       cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
                }
                else if (!strcmp(args[0], "off"))
                {
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