.write_memory = cortex_m3_write_memory,
.bulk_write_memory = cortex_m3_bulk_write_memory,
.checksum_memory = armv7m_checksum_memory,
+ .blank_check_memory = armv7m_blank_check_memory,
.run_algorithm = armv7m_run_algorithm,
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ int assert_srst = 1;
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
- if (target->reset_mode == RESET_RUN)
+ if (!target->reset_halt)
{
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m3->dcb_dhcsr & C_MASKINTS)
if (strcmp(cortex_m3->variant, "lm3s") == 0)
{
- /* this causes the luminary device to reset using the watchdog */
- ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ );
- LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
+ /* get revision of lm3s target, only early silicon has this issue
+ * Fury Rev B, DustDevil Rev B, Tempest all ok */
+
+ u32 did0;
+
+ if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
+ {
+ switch ((did0 >> 16) & 0xff)
+ {
+ case 0:
+ /* all Sandstorm suffer issue */
+ assert_srst = 0;
+ break;
+
+ case 1:
+ case 3:
+ /* only Fury/DustDevil rev A suffer reset problems */
+ if (((did0 >> 8) & 0xff) == 0)
+ assert_srst = 0;
+ break;
+ }
+ }
}
- else
+
+ if (assert_srst)
{
+ /* default to asserting srst */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
jtag_add_reset(1, 1);
jtag_add_reset(0, 1);
}
}
+ else
+ {
+ /* this causes the luminary device to reset using the watchdog */
+ ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ );
+ LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
+ }
target->state = TARGET_RESET;
jtag_add_sleep(50000);
return ERROR_OK;
}
-
int cortex_m3_quit()
{
variant = args[4];
cortex_m3_init_arch_info(target, cortex_m3, chain_pos, variant);
- cortex_m3_register_commands(cmd_ctx);
return ERROR_OK;
}
return retval;
}
-