reg_value = dsp563xx->core_regs[num];
buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
- dsp563xx->core_cache->reg_list[num].valid = 1;
- dsp563xx->core_cache->reg_list[num].dirty = 0;
+ dsp563xx->core_cache->reg_list[num].valid = true;
+ dsp563xx->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32);
dsp563xx->core_regs[num] = reg_value;
- dsp563xx->core_cache->reg_list[num].valid = 1;
- dsp563xx->core_cache->reg_list[num].dirty = 0;
+ dsp563xx->core_cache->reg_list[num].valid = true;
+ dsp563xx->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, reg->size, value);
- reg->dirty = 1;
- reg->valid = 1;
+ reg->dirty = true;
+ reg->valid = true;
return ERROR_OK;
}
reg_list[i].name = dsp563xx_regs[i].name;
reg_list[i].size = 32; /* dsp563xx_regs[i].bits; */
reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
+ reg_list[i].dirty = false;
+ reg_list[i].valid = false;
reg_list[i].type = &dsp563xx_reg_type;
reg_list[i].arch_info = &arch_info[i];
}
if (err != ERROR_OK)
return err;
/* r0 is no longer valid on target */
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
return ERROR_OK;
}
return err;
/* r0 is no longer valid on target */
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
return ERROR_OK;
}
struct dsp563xx_core_reg *arch_info;
if (force)
- dsp563xx->core_cache->reg_list[num].valid = 0;
+ dsp563xx->core_cache->reg_list[num].valid = false;
if (!dsp563xx->core_cache->reg_list[num].valid) {
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
struct dsp563xx_core_reg *arch_info;
if (force)
- dsp563xx->core_cache->reg_list[num].dirty = 1;
+ dsp563xx->core_cache->reg_list[num].dirty = true;
if (dsp563xx->core_cache->reg_list[num].dirty) {
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
if ((arch_info->instr_mask >= addr_start) &&
(arch_info->instr_mask <= addr_end)) {
- dsp563xx->core_cache->reg_list[i].valid = 0;
- dsp563xx->core_cache->reg_list[i].dirty = 0;
+ dsp563xx->core_cache->reg_list[i].valid = false;
+ dsp563xx->core_cache->reg_list[i].dirty = false;
}
}
}
err = dsp563xx_once_execute_dw_ir(target->tap, 1, arch_info->instr_mask, sr);
if (err != ERROR_OK)
return err;
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = true;
}
err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N0, 0);
if (err != ERROR_OK)
return err;
}
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = true;
if (dsp563xx->core_regs[DSP563XX_REG_IDX_N1] != 0x000000) {
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info;
if (err != ERROR_OK)
return err;
}
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = true;
if (dsp563xx->core_regs[DSP563XX_REG_IDX_M0] != 0xffffff) {
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info;
if (err != ERROR_OK)
return err;
}
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = true;
if (dsp563xx->core_regs[DSP563XX_REG_IDX_M1] != 0xffffff) {
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info;
if (err != ERROR_OK)
return err;
}
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = true;
err = dsp563xx_save_context(target);
if (err != ERROR_OK)
static int dsp563xx_resume(struct target *target,
int current,
- uint32_t address,
+ target_addr_t address,
int handle_breakpoints,
int debug_execution)
{
static int dsp563xx_step(struct target *target,
int current,
- uint32_t address,
+ target_addr_t address,
int handle_breakpoints)
{
int err;
static int dsp563xx_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
int timeout_ms, void *arch_info)
{
int i;
}
for (i = 0; i < num_mem_params; i++) {
+ if (mem_params[i].direction == PARAM_IN)
+ continue;
retval = target_write_buffer(target, mem_params[i].address,
mem_params[i].size, mem_params[i].value);
if (retval != ERROR_OK)
}
for (i = 0; i < num_reg_params; i++) {
+ if (reg_params[i].direction == PARAM_IN)
+ continue;
+
struct reg *reg = register_get_by_name(dsp563xx->core_cache,
reg_params[i].reg_name,
0);
dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
/* r0 is no longer valid on target */
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
/* r1 is no longer valid on target */
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
x = count;
b = buffer;
static int dsp563xx_read_memory(struct target *target,
int mem_type,
- uint32_t address,
+ target_addr_t address,
uint32_t size,
uint32_t count,
uint8_t *buffer)
}
static int dsp563xx_read_memory_default(struct target *target,
- uint32_t address,
+ target_addr_t address,
uint32_t size,
uint32_t count,
uint8_t *buffer)
}
static int dsp563xx_read_buffer_default(struct target *target,
- uint32_t address,
+ target_addr_t address,
uint32_t size,
uint8_t *buffer)
{
static int dsp563xx_write_memory_core(struct target *target,
int mem_type,
- uint32_t address,
+ target_addr_t address,
uint32_t size,
uint32_t count,
const uint8_t *buffer)
const uint8_t *b;
LOG_DEBUG(
- "memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
+ "memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mem_type,
address,
size,
dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
/* r0 is no longer valid on target */
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
/* r1 is no longer valid on target */
- dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1;
+ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
x = count;
b = buffer;
static int dsp563xx_write_memory(struct target *target,
int mem_type,
- uint32_t address,
+ target_addr_t address,
uint32_t size,
uint32_t count,
const uint8_t *buffer)
}
static int dsp563xx_write_memory_default(struct target *target,
- uint32_t address,
+ target_addr_t address,
uint32_t size,
uint32_t count,
const uint8_t *buffer)
}
static int dsp563xx_write_buffer_default(struct target *target,
- uint32_t address,
+ target_addr_t address,
uint32_t size,
const uint8_t *buffer)
{