return retval;
}
-int switch_tap(struct target * target, struct jtag_tap * master_tap,struct jtag_tap * core_tap){
+static int switch_tap(struct target * target, struct jtag_tap * master_tap,struct jtag_tap * core_tap){
int retval = ERROR_OK;
uint32_t instr;
uint32_t ir_out;//not used, just to make jtag happy.
return retval;
}
+/**
+ * Puts the core into debug mode, enabling the EOnCE module.
+ * This will not always work, eonce_enter_debug_mode executes much
+ * more complicated routine, which is guaranteed to work, but requires
+ * a reset. This will complicate comm with the flash module, since
+ * after a reset clock divisors must be set again.
+ * This implementation works most of the time, and is not accesible to the
+ * user.
+ *
+ * @param target
+ * @param eonce_status Data read from the EOnCE status register.
+ *
+ * @return
+ */
+static int eonce_enter_debug_mode_without_reset(struct target * target, uint16_t * eonce_status){
+ int retval;
+ uint32_t instr = JTAG_INSTR_DEBUG_REQUEST;
+ uint32_t ir_out;//not used, just to make jtag happy.
+ // Debug request #1
+ retval = dsp5680xx_irscan(target,& instr,& ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
+ err_check_propagate(retval);
+
+ // Enable EOnCE module
+ instr = JTAG_INSTR_ENABLE_ONCE;
+ //Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
+ err_check_propagate(retval);
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
+ err_check_propagate(retval);
+ // Verify that debug mode is enabled
+ uint16_t data_read_from_dr;
+ retval = eonce_read_status_reg(target,&data_read_from_dr);
+ err_check_propagate(retval);
+ if((data_read_from_dr&0x30) == 0x30){
+ LOG_DEBUG("EOnCE successfully entered debug mode.");
+ target->state = TARGET_HALTED;
+ retval = ERROR_OK;
+ }else{
+ retval = ERROR_TARGET_FAILURE;
+ err_check(retval,"Failed to set EOnCE module to debug mode. Try with halt");
+ }
+ if(eonce_status!=NULL)
+ *eonce_status = data_read_from_dr;
+ return ERROR_OK;
+}
+
#define TIME_DIV_FREESCALE 0.3
/**
* Puts the core into debug mode, enabling the EOnCE module.
uint16_t instr_16;
uint16_t read_16;
+ // First try the easy way
+ retval = eonce_enter_debug_mode_without_reset(target,eonce_status);
+ if(retval == ERROR_OK)
+ return retval;
+
struct jtag_tap * tap_chp;
struct jtag_tap * tap_cpu;
tap_chp = jtag_tap_by_string("dsp568013.chp");
instr = MASTER_TAP_CMD_IDCODE;
retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_MASTER_TAP_IRLEN);
err_check_propagate(retval);
- usleep(TIME_DIV_FREESCALE*100*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*100*1000);
// Enable EOnCE module
jtag_add_reset(0,1);
- usleep(TIME_DIV_FREESCALE*200*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*200*1000);
instr = 0x0606ffff;// This was selected experimentally.
retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,32);
err_check_propagate(retval);
retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
instr_16 = 0x20;
retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
- usleep(TIME_DIV_FREESCALE*100*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*100*1000);
jtag_add_reset(0,0);
- usleep(TIME_DIV_FREESCALE*300*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*300*1000);
instr = JTAG_INSTR_ENABLE_ONCE;
//Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
return retval;
}
-/**
- * Puts the core into debug mode, enabling the EOnCE module.
- * This will not always work, eonce_enter_debug_mode executes much
- * more complicated routine, which is guaranteed to work, but requires
- * a reset. This will complicate comm with the flash module, since
- * after a reset clock divisors must be set again.
- * This implementation works most of the time, and is not accesible to the
- * user.
- *
- * @param target
- * @param eonce_status Data read from the EOnCE status register.
- *
- * @return
- */
-static int eonce_enter_debug_mode_without_reset(struct target * target, uint16_t * eonce_status){
- int retval;
- uint32_t instr = JTAG_INSTR_DEBUG_REQUEST;
- uint32_t ir_out;//not used, just to make jtag happy.
- // Debug request #1
- retval = dsp5680xx_irscan(target,& instr,& ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
- err_check_propagate(retval);
-
- // Enable EOnCE module
- instr = JTAG_INSTR_ENABLE_ONCE;
- //Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
- retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
- err_check_propagate(retval);
- retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
- err_check_propagate(retval);
- // Verify that debug mode is enabled
- uint16_t data_read_from_dr;
- retval = eonce_read_status_reg(target,&data_read_from_dr);
- err_check_propagate(retval);
- if((data_read_from_dr&0x30) == 0x30){
- LOG_DEBUG("EOnCE successfully entered debug mode.");
- target->state = TARGET_HALTED;
- retval = ERROR_OK;
- }else{
- retval = ERROR_TARGET_FAILURE;
- err_check(retval,"Failed to set EOnCE module to debug mode. Try with halt");
- }
- if(eonce_status!=NULL)
- *eonce_status = data_read_from_dr;
- return ERROR_OK;
-}
-
/**
* Reads the current value of the program counter and stores it.
*
}
// Reset state machine
-int reset_jtag(void){
+static int reset_jtag(void){
int retval;
tap_state_t states[2];
const char *cp = "RESET";
}
jtag_add_reset(0,1);
- usleep(TIME_DIV_FREESCALE*200*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*200*1000);
retval = reset_jtag();
err_check(retval,"Failed to reset JTAG state machine");
- usleep(150);
+ jtag_add_sleep(150);
// Enable core tap
tap_chp->enabled = true;
instr = JTAG_INSTR_DEBUG_REQUEST;
retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
err_check_propagate(retval);
- usleep(TIME_DIV_FREESCALE*100*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*100*1000);
jtag_add_reset(0,0);
- usleep(TIME_DIV_FREESCALE*300*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*300*1000);
// Enable master tap
tap_chp->enabled = false;
retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,16);
err_check_propagate(retval);
- usleep(TIME_DIV_FREESCALE*150*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*150*1000);
jtag_add_reset(0,1);
- usleep(TIME_DIV_FREESCALE*200*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*200*1000);
retval = reset_jtag();
err_check(retval,"Failed to reset JTAG state machine");
- usleep(150);
+ jtag_add_sleep(150);
instr = 0x0606ffff;
retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,32);
retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
instr_16 = 0x20;
retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
- usleep(TIME_DIV_FREESCALE*100*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*100*1000);
jtag_add_reset(0,0);
- usleep(TIME_DIV_FREESCALE*300*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*300*1000);
return retval;
}
err_check_propagate(retval);
jtag_add_reset(0,1);
- usleep(TIME_DIV_FREESCALE*200*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*200*1000);
retval = reset_jtag();
err_check(retval,"Failed to reset JTAG state machine");
- usleep(TIME_DIV_FREESCALE*100*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*100*1000);
jtag_add_reset(0,0);
- usleep(TIME_DIV_FREESCALE*300*1000);
+ jtag_add_sleep(TIME_DIV_FREESCALE*300*1000);
return retval;
}