* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
+ * Copyright (C) 2007,2008 Øyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
{
+ int retval;
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
reg_t *reg_list = NULL;
embeddedice_reg_t *arch_info = NULL;
/* identify EmbeddedICE version by reading DCC control register */
embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
- jtag_execute_queue();
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ {
+ for (i = 0; i < num_regs; i++)
+ {
+ free(reg_list[i].value);
+ }
+ free(reg_list);
+ free(arch_info);
+ return NULL;
+ }
eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
arm7_9->has_single_step = 1;
break;
case 3:
- ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
+ LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
arm7_9->has_monitor_mode = 1;
break;
case 7:
- WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
+ LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
break;
default:
- ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
+ LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
}
+ return reg_cache;
+}
+
+int embeddedice_setup(target_t *target)
+{
+ int retval;
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+
/* explicitly disable monitor mode */
if (arm7_9->has_monitor_mode)
{
- embeddedice_read_reg(®_list[EICE_DBG_CTRL]);
- jtag_execute_queue();
- buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
- embeddedice_set_reg_w_exec(®_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value);
+ reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+
+ embeddedice_read_reg(dbg_ctrl);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ buf_set_u32(dbg_ctrl->value, 4, 1, 0);
+ embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
}
-
- return reg_cache;
+ return jtag_execute_queue();
}
int embeddedice_get_reg(reg_t *reg)
{
if (embeddedice_read_reg(reg) != ERROR_OK)
{
- ERROR("BUG: error scheduling EmbeddedICE register read");
+ LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
exit(-1);
}
if (jtag_execute_queue() != ERROR_OK)
{
- ERROR("register read failed");
+ LOG_ERROR("register read failed");
}
return ERROR_OK;
u8 field1_out[1];
u8 field2_out[1];
- DEBUG("%i", ice_reg->addr);
-
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(ice_reg->jtag_info, 0x2);
{
if (embeddedice_write_reg(reg, value) != ERROR_OK)
{
- ERROR("BUG: error scheduling EmbeddedICE register write");
+ LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
exit(-1);
}
if (jtag_execute_queue() != ERROR_OK)
{
- ERROR("register write failed");
+ LOG_ERROR("register write failed");
exit(-1);
}
return ERROR_OK;
{
embeddedice_reg_t *ice_reg = reg->arch_info;
- DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
+ LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(ice_reg->jtag_info, 0x2);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
- embeddedice_write_reg_inner(reg, value);
+ u8 reg_addr = ice_reg->addr & 0x1f;
+ embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
return ERROR_OK;
}