* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
-#include "armv4_5.h"
+#include "arm.h"
#include "etm.h"
#include "etb.h"
#include "register.h"
-
-static char* etb_reg_list[] =
-{
+static const char * const etb_reg_list[] = {
"ETB_identification",
"ETB_ram_depth",
"ETB_ram_width",
if (tap == NULL)
return ERROR_FAIL;
- if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
- {
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
struct scan_field field;
- field.tap = tap;
field.num_bits = tap->ir_length;
- field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
- buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
+ void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
+ field.out_value = t;
+ buf_set_u32(t, 0, field.num_bits, new_instr);
field.in_value = NULL;
- jtag_add_ir_scan(1, &field, jtag_get_end_state());
+ jtag_add_ir_scan(tap, &field, TAP_IDLE);
- free(field.out_value);
+ free(t);
}
return ERROR_OK;
static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
{
- if (etb->cur_scan_chain != new_scan_chain)
- {
+ if (etb->cur_scan_chain != new_scan_chain) {
struct scan_field field;
- field.tap = etb->tap;
field.num_bits = 5;
- field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
- buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
+ void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
+ field.out_value = t;
+ buf_set_u32(t, 0, field.num_bits, new_scan_chain);
field.in_value = NULL;
/* select INTEST instruction */
etb_set_instr(etb, 0x2);
- jtag_add_dr_scan(1, &field, jtag_get_end_state());
+ jtag_add_dr_scan(etb->tap, 1, &field, TAP_IDLE);
etb->cur_scan_chain = new_scan_chain;
- free(field.out_value);
+ free(t);
}
return ERROR_OK;
{
int retval;
- if ((retval = etb_read_reg(reg)) != ERROR_OK)
- {
+ retval = etb_read_reg(reg);
+ if (retval != ERROR_OK) {
LOG_ERROR("BUG: error scheduling ETB register read");
return retval;
}
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
LOG_ERROR("ETB register read failed");
return retval;
}
.set = etb_set_reg_w_exec,
};
-struct reg_cache* etb_build_reg_cache(struct etb *etb)
+struct reg_cache *etb_build_reg_cache(struct etb *etb)
{
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = NULL;
reg_cache->num_regs = num_regs;
/* set up registers */
- for (i = 0; i < num_regs; i++)
- {
+ for (i = 0; i < num_regs; i++) {
reg_list[i].name = etb_reg_list[i];
reg_list[i].size = 32;
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
+ reg_list[i].dirty = false;
+ reg_list[i].valid = false;
reg_list[i].value = calloc(1, 4);
reg_list[i].arch_info = &arch_info[i];
reg_list[i].type = &etb_reg_type;
{
uint8_t *in = (uint8_t *)arg;
- *((uint32_t *)in) = buf_get_u32(in, 0, 32);
+ *((uint32_t *)arg) = buf_get_u32(in, 0, 32);
}
-
static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
{
struct scan_field fields[3];
int i;
- jtag_set_end_state(TAP_IDLE);
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
- fields[0].tap = etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
- fields[1].tap = etb->tap;
fields[1].num_bits = 7;
- fields[1].out_value = malloc(1);
- buf_set_u32(fields[1].out_value, 0, 7, 4);
+ uint8_t temp1;
+ fields[1].out_value = &temp1;
+ buf_set_u32(&temp1, 0, 7, 4);
fields[1].in_value = NULL;
- fields[2].tap = etb->tap;
fields[2].num_bits = 1;
- fields[2].out_value = malloc(1);
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ uint8_t temp2;
+ fields[2].out_value = &temp2;
+ buf_set_u32(&temp2, 0, 1, 0);
fields[2].in_value = NULL;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
- for (i = 0; i < num_frames; i++)
- {
- /* ensure nR/W reamins set to read */
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ for (i = 0; i < num_frames; i++) {
+ /* ensure nR/W remains set to read */
+ buf_set_u32(&temp2, 0, 1, 0);
/* address remains set to 0x4 (RAM data) until we read the last frame */
if (i < num_frames - 1)
- buf_set_u32(fields[1].out_value, 0, 7, 4);
+ buf_set_u32(&temp1, 0, 7, 4);
else
- buf_set_u32(fields[1].out_value, 0, 7, 0);
+ buf_set_u32(&temp1, 0, 7, 0);
fields[0].in_value = (uint8_t *)(data + i);
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
}
jtag_execute_queue();
- free(fields[1].out_value);
- free(fields[2].out_value);
-
return ERROR_OK;
}
static int etb_read_reg_w_check(struct reg *reg,
- uint8_t* check_value, uint8_t* check_mask)
+ uint8_t *check_value, uint8_t *check_mask)
{
struct etb_reg *etb_reg = reg->arch_info;
uint8_t reg_addr = etb_reg->addr & 0x7f;
LOG_DEBUG("%i", (int)(etb_reg->addr));
- jtag_set_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
- fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].in_value = NULL;
fields[0].check_value = NULL;
fields[0].check_mask = NULL;
- fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
- fields[1].out_value = malloc(1);
- buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+ uint8_t temp1;
+ fields[1].out_value = &temp1;
+ buf_set_u32(&temp1, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[1].check_value = NULL;
fields[1].check_mask = NULL;
- fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
- fields[2].out_value = malloc(1);
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ uint8_t temp2;
+ fields[2].out_value = &temp2;
+ buf_set_u32(&temp2, 0, 1, 0);
fields[2].in_value = NULL;
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
/* read the identification register in the second run, to make sure we
* don't read the ETB data register twice, skipping every second entry
*/
- buf_set_u32(fields[1].out_value, 0, 7, 0x0);
+ buf_set_u32(&temp1, 0, 7, 0x0);
fields[0].in_value = reg->value;
fields[0].check_value = check_value;
fields[0].check_mask = check_mask;
- jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
-
- free(fields[1].out_value);
- free(fields[2].out_value);
+ jtag_add_dr_scan_check(etb_reg->etb->tap, 3, fields, TAP_IDLE);
return ERROR_OK;
}
{
int retval;
- if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
- {
+ retval = etb_write_reg(reg, value);
+ if (retval != ERROR_OK) {
LOG_ERROR("BUG: error scheduling ETB register write");
return retval;
}
buf_set_u32(reg->value, 0, reg->size, value);
- reg->valid = 1;
- reg->dirty = 0;
+ reg->valid = true;
+ reg->dirty = false;
return ERROR_OK;
}
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
LOG_ERROR("ETB: register write failed");
return retval;
}
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
- jtag_set_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
- fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
- fields[0].out_value = malloc(4);
- buf_set_u32(fields[0].out_value, 0, 32, value);
+ uint8_t temp0[4];
+ fields[0].out_value = temp0;
+ buf_set_u32(temp0, 0, 32, value);
fields[0].in_value = NULL;
- fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
- fields[1].out_value = malloc(1);
- buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+ uint8_t temp1;
+ fields[1].out_value = &temp1;
+ buf_set_u32(&temp1, 0, 7, reg_addr);
fields[1].in_value = NULL;
- fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
- fields[2].out_value = malloc(1);
- buf_set_u32(fields[2].out_value, 0, 1, 1);
-
+ uint8_t temp2;
+ fields[2].out_value = &temp2;
+ buf_set_u32(&temp2, 0, 1, 1);
fields[2].in_value = NULL;
- free(fields[0].out_value);
- free(fields[1].out_value);
- free(fields[2].out_value);
+ jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
return ERROR_OK;
}
struct arm *arm;
if (CMD_ARGC != 2)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
target = get_target(CMD_ARGV[0]);
- if (!target)
- {
+ if (!target) {
LOG_ERROR("ETB: target '%s' not defined", CMD_ARGV[0]);
return ERROR_FAIL;
}
arm = target_to_arm(target);
- if (!is_arm(arm))
- {
- command_print(cmd_ctx, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
+ if (!is_arm(arm)) {
+ command_print(CMD_CTX, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
return ERROR_FAIL;
}
tap = jtag_tap_by_string(CMD_ARGV[1]);
- if (tap == NULL)
- {
- command_print(cmd_ctx, "ETB: TAP %s does not exist", CMD_ARGV[1]);
+ if (tap == NULL) {
+ command_print(CMD_CTX, "ETB: TAP %s does not exist", CMD_ARGV[1]);
return ERROR_FAIL;
}
- if (arm->etm)
- {
+ if (arm->etm) {
struct etb *etb = malloc(sizeof(struct etb));
arm->etm->capture_driver_priv = etb;
etb->reg_cache = NULL;
etb->ram_width = 0;
etb->ram_depth = 0;
- }
- else
- {
+ } else {
LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
return ERROR_FAIL;
}
return ERROR_OK;
}
-static int etb_register_commands(struct command_context *cmd_ctx)
+COMMAND_HANDLER(handle_etb_trigger_percent_command)
{
- struct command *etb_cmd = register_command(cmd_ctx, NULL, "etb",
- NULL, COMMAND_ANY, "Embedded Trace Buffer");
+ struct target *target;
+ struct arm *arm;
+ struct etm_context *etm;
+ struct etb *etb;
- register_command(cmd_ctx, etb_cmd, "config",
- handle_etb_config_command, COMMAND_CONFIG,
- NULL);
+ target = get_current_target(CMD_CTX);
+ arm = target_to_arm(target);
+ if (!is_arm(arm)) {
+ command_print(CMD_CTX, "ETB: current target isn't an ARM");
+ return ERROR_FAIL;
+ }
+
+ etm = arm->etm;
+ if (!etm) {
+ command_print(CMD_CTX, "ETB: target has no ETM configured");
+ return ERROR_FAIL;
+ }
+ if (etm->capture_driver != &etb_capture_driver) {
+ command_print(CMD_CTX, "ETB: target not using ETB");
+ return ERROR_FAIL;
+ }
+ etb = arm->etm->capture_driver_priv;
+
+ if (CMD_ARGC > 0) {
+ uint32_t new_value;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
+ if ((new_value < 2) || (new_value > 100))
+ command_print(CMD_CTX,
+ "valid percentages are 2%% to 100%%");
+ else
+ etb->trigger_percent = (unsigned) new_value;
+ }
+
+ command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger",
+ etb->trigger_percent);
return ERROR_OK;
}
+static const struct command_registration etb_config_command_handlers[] = {
+ {
+ /* NOTE: with ADIv5, ETBs are accessed using DAP operations,
+ * possibly over SWD, not through separate TAPs...
+ */
+ .name = "config",
+ .handler = handle_etb_config_command,
+ .mode = COMMAND_CONFIG,
+ .help = "Associate ETB with target and JTAG TAP.",
+ .usage = "target tap",
+ },
+ {
+ .name = "trigger_percent",
+ .handler = handle_etb_trigger_percent_command,
+ .mode = COMMAND_EXEC,
+ .help = "Set percent of trace buffer to be filled "
+ "after the trigger occurs (2..100).",
+ .usage = "[percent]",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration etb_command_handlers[] = {
+ {
+ .name = "etb",
+ .mode = COMMAND_ANY,
+ .help = "Embedded Trace Buffer command group",
+ .chain = etb_config_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
static int etb_init(struct etm_context *etm_ctx)
{
struct etb *etb = etm_ctx->capture_driver_priv;
etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
+ etb->trigger_percent = 50;
+
return ERROR_OK;
}
* i.e. don't read invalid entries
*/
if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
- {
- first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
- }
+ first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value,
+ 0,
+ 32);
else
- {
- num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
- }
+ num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value,
+ 0,
+ 32);
etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
etb_read_ram(etb, trace_data, num_frames);
if (etm_ctx->trace_depth > 0)
- {
free(etm_ctx->trace_data);
- }
- if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
+ if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
etm_ctx->trace_depth = num_frames * 3;
- else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
+ else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
etm_ctx->trace_depth = num_frames * 2;
else
etm_ctx->trace_depth = num_frames;
etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
- for (i = 0, j = 0; i < num_frames; i++)
- {
- if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
- {
+ for (i = 0, j = 0; i < num_frames; i++) {
+ if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT) {
/* trace word j */
etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
etm_ctx->trace_data[j].flags = 0;
if ((trace_data[i] & 0x80) >> 7)
- {
etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
- }
- if (etm_ctx->trace_data[j].pipestat == STAT_TR)
- {
- etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
+ if (etm_ctx->trace_data[j].pipestat == STAT_TR) {
+ etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet &
+ 0x7;
etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
}
etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
etm_ctx->trace_data[j + 1].flags = 0;
if ((trace_data[i] & 0x8000) >> 15)
- {
etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
- }
- if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
- {
- etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+ if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) {
+ etm_ctx->trace_data[j +
+ 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
}
etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
etm_ctx->trace_data[j + 2].flags = 0;
if ((trace_data[i] & 0x800000) >> 23)
- {
etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
- }
- if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
- {
- etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
+ if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR) {
+ etm_ctx->trace_data[j +
+ 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
}
j += 3;
- }
- else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
- {
+ } else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) {
/* trace word j */
etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
etm_ctx->trace_data[j].flags = 0;
if ((trace_data[i] & 0x800) >> 11)
- {
etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
- }
- if (etm_ctx->trace_data[j].pipestat == STAT_TR)
- {
- etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
+ if (etm_ctx->trace_data[j].pipestat == STAT_TR) {
+ etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet &
+ 0x7;
etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
}
etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
etm_ctx->trace_data[j + 1].flags = 0;
if ((trace_data[i] & 0x800000) >> 23)
- {
etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
- }
- if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
- {
- etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+ if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) {
+ etm_ctx->trace_data[j +
+ 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
}
j += 2;
- }
- else
- {
+ } else {
/* trace word j */
etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
etm_ctx->trace_data[j].flags = 0;
if ((trace_data[i] & 0x80000) >> 19)
- {
etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
- }
- if (etm_ctx->trace_data[j].pipestat == STAT_TR)
- {
- etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
+ if (etm_ctx->trace_data[j].pipestat == STAT_TR) {
+ etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet &
+ 0x7;
etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
}
uint32_t etb_ctrl_value = 0x1;
uint32_t trigger_count;
- if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
- {
- if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
- {
+ if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED) {
+ if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT) {
LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
}
etb_ctrl_value |= 0x2;
}
- if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
+ if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
LOG_ERROR("ETB: can't run in multiplexed mode");
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
}
- trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
+ trigger_count = (etb->ram_depth * etb->trigger_percent) / 100;
etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
return ERROR_OK;
}
-struct etm_capture_driver etb_capture_driver =
-{
+struct etm_capture_driver etb_capture_driver = {
.name = "etb",
- .register_commands = etb_register_commands,
+ .commands = etb_command_handlers,
.init = etb_init,
.status = etb_status,
.start_capture = etb_start_capture,
Code Review / openocd.git / blobdiff