#endif
#include "armv4_5.h"
+#include "etm.h"
#include "etb.h"
#include "image.h"
#include "arm_disassembler.h"
+#include "register.h"
/*
* ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
*/
-#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
-
enum {
RO, /* read/only */
WO, /* write/only */
{ 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
#endif
-static int etm_reg_arch_type = -1;
-
static int etm_get_reg(struct reg *reg);
static int etm_read_reg_w_check(struct reg *reg,
uint8_t* check_value, uint8_t* check_mask);
-static int etm_register_user_commands(struct command_context_s *cmd_ctx);
+static int etm_register_user_commands(struct command_context *cmd_ctx);
static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
static int etm_write_reg(struct reg *reg, uint32_t value);
-static command_t *etm_cmd;
+static struct command *etm_cmd;
+static const struct reg_arch_type etm_scan6_type = {
+ .get = etm_get_reg,
+ .set = etm_set_reg_w_exec,
+};
/* Look up register by ID ... most ETM instances only
* support a subset of the possible registers.
reg->size = r->size;
reg->value = &ereg->value;
reg->arch_info = ereg;
- reg->arch_type = etm_reg_arch_type;
+ reg->type = &etm_scan6_type;
reg++;
cache->num_regs++;
struct etm_reg *arch_info = NULL;
unsigned bcd_vers, config;
- /* register a register arch-type for etm registers only once */
- if (etm_reg_arch_type == -1)
- etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
- etm_set_reg_w_exec);
-
/* the actual registers are kept in two arrays */
reg_list = calloc(128, sizeof(struct reg));
arch_info = calloc(128, sizeof(struct etm_reg));
break;
default:
LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
- free(reg_cache);
- free(reg_list);
- free(arch_info);
- return ERROR_OK;
+ goto fail;
}
}
etm_ctx->bcd_vers = bcd_vers;
if (!etb)
{
LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
- free(reg_cache);
- free(reg_list);
- free(arch_info);
- return ERROR_OK;
+ goto fail;
}
reg_cache->next = etb_build_reg_cache(etb);
etm_ctx->reg_cache = reg_cache;
return reg_cache;
+
+fail:
+ free(reg_cache);
+ free(reg_list);
+ free(arch_info);
+ return NULL;
}
static int etm_read_reg(struct reg *reg)
{
int i;
int section = -1;
- uint32_t size_read;
+ size_t size_read;
uint32_t opcode;
int retval;
return 0;
}
-static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context_s *cmd_ctx)
+static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
{
int retval;
struct arm_instruction instruction;
return retval;
}
-int etm_register_commands(struct command_context_s *cmd_ctx)
+int etm_register_commands(struct command_context *cmd_ctx)
{
etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
return ERROR_OK;
}
-static int etm_register_user_commands(struct command_context_s *cmd_ctx)
+static int etm_register_user_commands(struct command_context *cmd_ctx)
{
register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
COMMAND_EXEC, "configure/display trace mode: "