cross compile fix

[openocd.git] / src / target / event / str912_reset.script

diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script
index 8178c82c702f987d4e2834858951a3a02913ac6e..33c62047183ad275e145936e812dbdcbc808bae3 100644 (file)
--- a/src/target/event/str912_reset.script
+++ b/src/target/event/str912_reset.script
@@ -1,21 +1,5 @@
-mww 0xFFFFFD44, 0x00008000 #Disable watchdog\r
-mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator\r
-sleep 20\r
-mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR\r
-sleep 20\r
-\r
-\r
-# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,\r
-#    when the bank 0 is the boot bank, then enable the Bank 1. */\r
-\r
-mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB\r
-mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB\r
-mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0\r
-mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000\r
-mww 0x54000018, 0x18 #Enable CS on both banks\r
-\r
-# -- Enable 96K RAM */\r
-mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled\r
-arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register\r
-\r
-flash protect 0 0 7 off\r
+# -- Enable 96K RAM */
+mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
+
+str9x flash_config 0 4 2 0 0x80000
+flash protect 0 0 7 off