}
static int adapter_load_core_reg_u32(struct target *target,
- enum armv7m_regtype type,
uint32_t num, uint32_t *value)
{
int retval;
}
static int adapter_store_core_reg_u32(struct target *target,
- enum armv7m_regtype type,
uint32_t num, uint32_t value)
{
int retval;
adapter_load_context(target);
/* make sure we clear the vector catch bit */
- adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 0);
+ adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
xPSR = buf_get_u32(r->value, 0, 32);
/* Are we in an exception handler */
if (xPSR & 0x1FF) {
- armv7m->core_mode = ARMV7M_MODE_HANDLER;
armv7m->exception_number = (xPSR & 0x1FF);
arm->core_mode = ARM_MODE_HANDLER;
arm->map = armv7m_msp_reg_map;
} else {
- unsigned control = buf_get_u32(armv7m->core_cache
+ unsigned control = buf_get_u32(arm->core_cache
->reg_list[ARMV7M_CONTROL].value, 0, 2);
/* is this thread privileged? */
- armv7m->core_mode = control & 1;
- arm->core_mode = armv7m->core_mode
+ arm->core_mode = control & 1
? ARM_MODE_USER_THREAD
: ARM_MODE_THREAD;
}
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
- armv7m_mode_strings[armv7m->core_mode],
+ arm_mode_name(arm->core_mode),
*(uint32_t *)(arm->pc->value),
target_state_name(target));
/* only set vector catch if halt is requested */
if (target->reset_halt)
- adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, VC_CORERESET);
+ adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA|VC_CORERESET);
else
- adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 0);
+ adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
if (jtag_reset_config & RESET_HAS_SRST) {
if (!srst_asserted) {
resume_pc = buf_get_u32(pc->value, 0, 32);
+ /* write any user vector flags */
+ res = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
+ if (res != ERROR_OK)
+ return res;
+
armv7m_restore_context(target);
/* registers are now invalid */