/*
- * Copyright(c) 2013 Intel Corporation.
+ * Copyright(c) 2013-2016 Intel Corporation.
*
* Adrian Burns (adrian.burns@intel.com)
* Thomas Faust (thomas.faust@intel.com)
* Ivan De Cesaris (ivan.de.cesaris@intel.com)
* Julien Carreno (julien.carreno@intel.com)
* Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
+ * Jessica Gomez (jessica.gomez.hernandez@intel.com)
*
* This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* Contact Information:
* Intel Corporation
}
for (i = 0; i < (x86_32->cache->num_regs); i++) {
- x86_32->cache->reg_list[i].dirty = 0;
- x86_32->cache->reg_list[i].valid = 0;
+ x86_32->cache->reg_list[i].dirty = false;
+ x86_32->cache->reg_list[i].valid = false;
}
return err;
}
struct target *t = lakemont_reg->target;
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
- LOG_DEBUG("reg=%s, value=%08" PRIx32, reg->name,
+ LOG_DEBUG("reg=%s, value=0x%08" PRIx32, reg->name,
buf_get_u32(reg->value, 0, 32));
return retval;
}
struct lakemont_core_reg *lakemont_reg = reg->arch_info;
struct target *t = lakemont_reg->target;
uint32_t value = buf_get_u32(buf, 0, 32);
- LOG_DEBUG("reg=%s, newval=%08" PRIx32, reg->name, value);
+ LOG_DEBUG("reg=%s, newval=0x%08" PRIx32, reg->name, value);
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value);
- reg->dirty = 1;
- reg->valid = 1;
+ reg->dirty = true;
+ reg->valid = true;
return ERROR_OK;
}
int num_regs = ARRAY_SIZE(regs);
struct reg_cache **cache_p = register_get_last_cache_p(&t->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
+ struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct lakemont_core_reg *arch_info = malloc(sizeof(struct lakemont_core_reg) * num_regs);
struct reg_feature *feature;
int i;
reg_list[i].name = regs[i].name;
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
+ reg_list[i].dirty = false;
+ reg_list[i].valid = false;
reg_list[i].type = &lakemont_reg_type;
reg_list[i].arch_info = &arch_info[i];
static int enter_probemode(struct target *t)
{
uint32_t tapstatus = 0;
+ int retries = 100;
+
tapstatus = get_tapstatus(t);
- LOG_DEBUG("TS before PM enter = %08" PRIx32, tapstatus);
+ LOG_DEBUG("TS before PM enter = 0x%08" PRIx32, tapstatus);
if (tapstatus & TS_PM_BIT) {
LOG_DEBUG("core already in probemode");
return ERROR_OK;
scan.out[0] = 1;
if (drscan(t, scan.out, scan.in, 1) != ERROR_OK)
return ERROR_FAIL;
- tapstatus = get_tapstatus(t);
- LOG_DEBUG("TS after PM enter = %08" PRIx32, tapstatus);
- if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT)))
- return ERROR_OK;
- else {
- LOG_ERROR("%s PM enter error, tapstatus = %08" PRIx32
- , __func__, tapstatus);
- return ERROR_FAIL;
+
+ while (retries--) {
+ tapstatus = get_tapstatus(t);
+ LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus);
+ if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT)))
+ return ERROR_OK;
}
+
+ LOG_ERROR("%s PM enter error, tapstatus = 0x%08" PRIx32
+ , __func__, tapstatus);
+ return ERROR_FAIL;
}
static int exit_probemode(struct target *t)
{
uint32_t tapstatus = get_tapstatus(t);
- LOG_DEBUG("TS before PM exit = %08" PRIx32, tapstatus);
+ LOG_DEBUG("TS before PM exit = 0x%08" PRIx32, tapstatus);
if (!(tapstatus & TS_PM_BIT)) {
LOG_USER("core not in PM");
struct x86_32_common *x86_32 = target_to_x86_32(t);
if (write_hw_reg(t, DSB, PM_DSB, 0) != ERROR_OK)
return ERROR_FAIL;
- LOG_DEBUG("write %s %08" PRIx32, regs[DSB].name, PM_DSB);
+ LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSB].name, PM_DSB);
if (write_hw_reg(t, DSL, PM_DSL, 0) != ERROR_OK)
return ERROR_FAIL;
- LOG_DEBUG("write %s %08" PRIx32, regs[DSL].name, PM_DSL);
+ LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSL].name, PM_DSL);
if (write_hw_reg(t, DSAR, PM_DSAR, 0) != ERROR_OK)
return ERROR_FAIL;
- LOG_DEBUG("write DSAR %08" PRIx32, PM_DSAR);
+ LOG_DEBUG("write DSAR 0x%08" PRIx32, PM_DSAR);
+ if (write_hw_reg(t, CSB, PM_DSB, 0) != ERROR_OK)
+ return ERROR_FAIL;
+ LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSB].name, PM_DSB);
+ if (write_hw_reg(t, CSL, PM_DSL, 0) != ERROR_OK)
+ return ERROR_FAIL;
+ LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSL].name, PM_DSL);
if (write_hw_reg(t, DR7, PM_DR7, 0) != ERROR_OK)
return ERROR_FAIL;
- LOG_DEBUG("write DR7 %08" PRIx32, PM_DR7);
+ LOG_DEBUG("write DR7 0x%08" PRIx32, PM_DR7);
uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
uint32_t csar = buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32);
uint32_t cr0 = buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32);
/* clear VM86 and IF bits if they are set */
- LOG_DEBUG("EFLAGS = %08" PRIx32 ", VM86 = %d, IF = %d", eflags,
+ LOG_DEBUG("EFLAGS = 0x%08" PRIx32 ", VM86 = %d, IF = %d", eflags,
eflags & EFLAGS_VM86 ? 1 : 0,
eflags & EFLAGS_IF ? 1 : 0);
- if (eflags & EFLAGS_VM86
- || eflags & EFLAGS_IF) {
+ if ((eflags & EFLAGS_VM86) || (eflags & EFLAGS_IF)) {
x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF);
if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK)
return ERROR_FAIL;
- LOG_DEBUG("EFLAGS now = %08" PRIx32 ", VM86 = %d, IF = %d",
+ LOG_DEBUG("EFLAGS now = 0x%08" PRIx32 ", VM86 = %d, IF = %d",
x86_32->pm_regs[I(EFLAGS)],
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0,
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0);
x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL;
if (write_hw_reg(t, CSAR, x86_32->pm_regs[I(CSAR)], 0) != ERROR_OK)
return ERROR_FAIL;
- LOG_DEBUG("write CSAR_CPL to 0 %08" PRIx32, x86_32->pm_regs[I(CSAR)]);
+ LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);
}
if (ssar & SSAR_DPL) {
- x86_32->pm_regs[I(SSAR)] = ssar & ~CSAR_DPL;
+ x86_32->pm_regs[I(SSAR)] = ssar & ~SSAR_DPL;
if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK)
return ERROR_FAIL;
- LOG_DEBUG("write SSAR_CPL to 0 %08" PRIx32, x86_32->pm_regs[I(SSAR)]);
+ LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);
}
- /* if cache's are enabled, disable and flush */
- if (!(cr0 & CR0_CD)) {
- LOG_DEBUG("caching enabled CR0 = %08" PRIx32, cr0);
+ /* if cache's are enabled, disable and flush, depending on the core version */
+ if (!(x86_32->core_type == LMT3_5) && !(cr0 & CR0_CD)) {
+ LOG_DEBUG("caching enabled CR0 = 0x%08" PRIx32, cr0);
if (cr0 & CR0_PG) {
x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG;
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
return ERROR_FAIL;
- LOG_DEBUG("cleared paging CR0_PG = %08" PRIx32, x86_32->pm_regs[I(CR0)]);
+ LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
/* submit wbinvd to flush cache */
if (submit_reg_pir(t, WBINVD) != ERROR_OK)
return ERROR_FAIL;
x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG);
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
return ERROR_FAIL;
- LOG_DEBUG("set CD, NW and PG, CR0 = %08" PRIx32, x86_32->pm_regs[I(CR0)]);
+ LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
}
}
return ERROR_OK;
t->state = TARGET_DEBUG_RUNNING;
if (enter_probemode(t) != ERROR_OK)
return ERROR_FAIL;
+
+ return lakemont_update_after_probemode_entry(t);
+}
+
+/* we need to expose the update to be able to complete the reset at SoC level */
+int lakemont_update_after_probemode_entry(struct target *t)
+{
if (save_context(t) != ERROR_OK)
return ERROR_FAIL;
if (halt_prep(t) != ERROR_OK)
static int read_all_core_hw_regs(struct target *t)
{
int err;
- uint32_t regval, i;
+ uint32_t regval;
+ unsigned i;
struct x86_32_common *x86_32 = target_to_x86_32(t);
for (i = 0; i < (x86_32->cache->num_regs); i++) {
if (NOT_AVAIL_REG == regs[i].pm_idx)
return err;
}
}
- LOG_DEBUG("read_all_core_hw_regs read %d registers ok", i);
+ LOG_DEBUG("read_all_core_hw_regs read %u registers ok", i);
return ERROR_OK;
}
static int write_all_core_hw_regs(struct target *t)
{
int err;
- uint32_t i;
+ unsigned i;
struct x86_32_common *x86_32 = target_to_x86_32(t);
for (i = 0; i < (x86_32->cache->num_regs); i++) {
if (NOT_AVAIL_REG == regs[i].pm_idx)
return err;
}
}
- LOG_DEBUG("write_all_core_hw_regs wrote %d registers ok", i);
+ LOG_DEBUG("write_all_core_hw_regs wrote %u registers ok", i);
return ERROR_OK;
}
*regval = buf_get_u32(scan.out, 0, 32);
if (cache) {
buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
- x86_32->cache->reg_list[reg].valid = 1;
- x86_32->cache->reg_list[reg].dirty = 0;
+ x86_32->cache->reg_list[reg].valid = true;
+ x86_32->cache->reg_list[reg].dirty = false;
}
- LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=%08" PRIx32,
+ LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
x86_32->cache->reg_list[reg].name,
arch_info->op,
*regval);
if (cache)
regval = buf_get_u32(x86_32->cache->reg_list[reg].value, 0, 32);
buf_set_u32(reg_buf, 0, 32, regval);
- LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=%08" PRIx32,
+ LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
x86_32->cache->reg_list[reg].name,
arch_info->op,
regval);
- scan.out[0] = RDWRPDR;
x86_32->flush = 0; /* dont flush scans till we have a batch */
- if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
- return ERROR_FAIL;
- if (drscan(t, reg_buf, scan.out, PDR_SIZE) != ERROR_OK)
- return ERROR_FAIL;
if (submit_reg_pir(t, reg) != ERROR_OK)
return ERROR_FAIL;
if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
return ERROR_FAIL;
+ scan.out[0] = RDWRPDR;
+ if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
+ return ERROR_FAIL;
+ if (drscan(t, reg_buf, scan.out, PDR_SIZE) != ERROR_OK)
+ return ERROR_FAIL;
x86_32->flush = 1;
if (submit_instruction_pir(t, PDR2SRAM) != ERROR_OK)
return ERROR_FAIL;
/* we are writing from the cache so ensure we reset flags */
if (cache) {
- x86_32->cache->reg_list[reg].dirty = 0;
- x86_32->cache->reg_list[reg].valid = 0;
+ x86_32->cache->reg_list[reg].dirty = false;
+ x86_32->cache->reg_list[reg].valid = false;
}
return ERROR_OK;
}
{
uint32_t tapstatus = get_tapstatus(t);
if ((TS_EN_PM_BIT | TS_PRDY_BIT) & tapstatus) {
- LOG_ERROR("%s transaction error tapstatus = %08" PRIx32
+ LOG_ERROR("%s transaction error tapstatus = 0x%08" PRIx32
, __func__, tapstatus);
return ERROR_FAIL;
} else {
if ((ts & TS_PM_BIT) && (ts & TS_PMCR_BIT)) {
- LOG_DEBUG("redirect to PM, tapstatus=%08" PRIx32, get_tapstatus(t));
+ LOG_DEBUG("redirect to PM, tapstatus=0x%08" PRIx32, get_tapstatus(t));
t->state = TARGET_DEBUG_RUNNING;
if (save_context(t) != ERROR_OK)
uint32_t dr7 = buf_get_u32(x86_32->cache->reg_list[DR7].value, 0, 32);
uint32_t type = dr7 & (0x03 << (DR7_RW_SHIFT + hwbreakpoint*DR7_RW_LEN_SIZE));
if (type == DR7_BP_EXECUTE) {
- LOG_USER("hit hardware breakpoint (hwreg=%d) at 0x%08" PRIx32, hwbreakpoint, eip);
+ LOG_USER("hit hardware breakpoint (hwreg=%" PRIu32 ") at 0x%08" PRIx32, hwbreakpoint, eip);
} else {
uint32_t address = 0;
switch (hwbreakpoint) {
address = buf_get_u32(x86_32->cache->reg_list[DR3].value, 0, 32);
break;
}
- LOG_USER("hit '%s' watchpoint for 0x%08" PRIx32 " (hwreg=%d) at 0x%08" PRIx32,
+ LOG_USER("hit '%s' watchpoint for 0x%08" PRIx32 " (hwreg=%" PRIu32 ") at 0x%08" PRIx32,
type == DR7_BP_WRITE ? "write" : "access", address,
hwbreakpoint, eip);
}
* breakpoint instruction. This needs to be corrected.
*/
buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
- x86_32->cache->reg_list[EIP].dirty = 1;
- x86_32->cache->reg_list[EIP].valid = 1;
+ x86_32->cache->reg_list[EIP].dirty = true;
+ x86_32->cache->reg_list[EIP].valid = true;
LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
} else {
/* it's not a hardware breakpoint (checked already in DR6 state)
return target_call_event_callbacks(t, TARGET_EVENT_HALTED);
}
}
+
return ERROR_OK;
}
}
}
-int lakemont_resume(struct target *t, int current, uint32_t address,
+int lakemont_resume(struct target *t, int current, target_addr_t address,
int handle_breakpoints, int debug_execution)
{
struct breakpoint *bp = NULL;
}
int lakemont_step(struct target *t, int current,
- uint32_t address, int handle_breakpoints)
+ target_addr_t address, int handle_breakpoints)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
}
/* Set EFLAGS[TF] and PMCR[IR], exit pm and wait for PRDY# */
- LOG_DEBUG("modifying PMCR = %d and EFLAGS = %08" PRIx32, pmcr, eflags);
+ LOG_DEBUG("modifying PMCR = 0x%08" PRIx32 " and EFLAGS = 0x%08" PRIx32, pmcr, eflags);
eflags = eflags | (EFLAGS_TF | EFLAGS_RF);
buf_set_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32, eflags);
buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
- LOG_DEBUG("EFLAGS [TF] [RF] bits set=%08" PRIx32 ", PMCR=%d, EIP=%08" PRIx32,
+ LOG_DEBUG("EFLAGS [TF] [RF] bits set=0x%08" PRIx32 ", PMCR=0x%08" PRIx32 ", EIP=0x%08" PRIx32,
eflags, pmcr, eip);
tapstatus = get_tapstatus(t);
return retval;
}
-/* TODO - implement resetbreak fully through CLTAP registers */
+static int lakemont_reset_break(struct target *t)
+{
+ struct x86_32_common *x86_32 = target_to_x86_32(t);
+ struct jtag_tap *saved_tap = x86_32->curr_tap;
+ struct scan_field *fields = &scan.field;
+
+ int retval = ERROR_OK;
+
+ LOG_DEBUG("issuing port 0xcf9 reset");
+
+ /* prepare resetbreak setting the proper bits in CLTAPC_CPU_VPREQ */
+ x86_32->curr_tap = jtag_tap_by_position(1);
+ if (x86_32->curr_tap == NULL) {
+ x86_32->curr_tap = saved_tap;
+ LOG_ERROR("%s could not select quark_x10xx.cltap", __func__);
+ return ERROR_FAIL;
+ }
+
+ fields->in_value = NULL;
+ fields->num_bits = 8;
+
+ /* select CLTAPC_CPU_VPREQ instruction*/
+ scan.out[0] = 0x51;
+ fields->out_value = ((uint8_t *)scan.out);
+ jtag_add_ir_scan(x86_32->curr_tap, fields, TAP_IDLE);
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ x86_32->curr_tap = saved_tap;
+ LOG_ERROR("%s irscan failed to execute queue", __func__);
+ return retval;
+ }
+
+ /* set enable_preq_on_reset & enable_preq_on_reset2 bits*/
+ scan.out[0] = 0x06;
+ fields->out_value = ((uint8_t *)scan.out);
+ jtag_add_dr_scan(x86_32->curr_tap, 1, fields, TAP_IDLE);
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("%s drscan failed to execute queue", __func__);
+ x86_32->curr_tap = saved_tap;
+ return retval;
+ }
+
+ /* restore current tap */
+ x86_32->curr_tap = saved_tap;
+
+ return ERROR_OK;
+}
+
+/*
+ * If we ever get an adapter with support for PREQ# and PRDY#, we should
+ * update this function to add support for using those two signals.
+ *
+ * Meanwhile, we're assuming that we only support reset break.
+ */
int lakemont_reset_assert(struct target *t)
{
- LOG_DEBUG("-");
+ struct x86_32_common *x86_32 = target_to_x86_32(t);
+ /* write 0x6 to I/O port 0xcf9 to cause the reset */
+ uint8_t cf9_reset_val = 0x6;
+ int retval;
+
+ LOG_DEBUG(" ");
+
+ if (t->state != TARGET_HALTED) {
+ LOG_DEBUG("target must be halted first");
+ retval = lakemont_halt(t);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("could not halt target");
+ return retval;
+ }
+ x86_32->forced_halt_for_reset = true;
+ }
+
+ if (t->reset_halt) {
+ retval = lakemont_reset_break(t);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ retval = x86_32_common_write_io(t, 0xcf9, BYTE, &cf9_reset_val);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("could not write to port 0xcf9");
+ return retval;
+ }
+
+ if (!t->reset_halt && x86_32->forced_halt_for_reset) {
+ x86_32->forced_halt_for_reset = false;
+ retval = lakemont_resume(t, true, 0x00, false, true);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ /* remove breakpoints and watchpoints */
+ x86_32_common_reset_breakpoints_watchpoints(t);
+
return ERROR_OK;
}
int lakemont_reset_deassert(struct target *t)
{
- LOG_DEBUG("-");
+ int retval;
+
+ LOG_DEBUG(" ");
+
+ if (target_was_examined(t)) {
+ retval = lakemont_poll(t);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ if (t->reset_halt) {
+ /* entered PM after reset, update the state */
+ retval = lakemont_update_after_probemode_entry(t);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("could not update state after probemode entry");
+ return retval;
+ }
+
+ if (t->state != TARGET_HALTED) {
+ LOG_WARNING("%s: ran after reset and before halt ...",
+ target_name(t));
+ if (target_was_examined(t)) {
+ retval = target_halt(t);
+ if (retval != ERROR_OK)
+ return retval;
+ } else {
+ t->state = TARGET_UNKNOWN;
+ }
+ }
+ }
+
return ERROR_OK;
}
Code Review / openocd.git / blobdiff