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stlink: collapse consecutive mem AP r/w in a single command
[openocd.git] / src / target / lakemont.c
diff --git a/src/target/lakemont.c b/src/target/lakemont.c
index b81213ebde663189b278b1b7a417afbd6a8c6111..e46ee5cf83f09d29cd9170835e6c4212d2b336d2 100644 (file)
--- a/src/target/lakemont.c
+++ b/src/target/lakemont.c
@@ -227,7 +227,7 @@ static int irscan(struct target *t, uint8_t *out,
 {
        int retval = ERROR_OK;
        struct x86_32_common *x86_32 = target_to_x86_32(t);
-       if (NULL == t->tap) {
+       if (!t->tap) {
                retval = ERROR_FAIL;
                LOG_ERROR("%s invalid target tap", __func__);
                return retval;
@@ -260,7 +260,7 @@ static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len)
        int retval = ERROR_OK;
        uint64_t data = 0;
        struct x86_32_common *x86_32 = target_to_x86_32(t);
-       if (NULL == t->tap) {
+       if (!t->tap) {
                retval = ERROR_FAIL;
                LOG_ERROR("%s invalid target tap", __func__);
                return retval;
@@ -283,7 +283,7 @@ static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len)
                        return retval;
                }
        }
-       if (in != NULL) {
+       if (in) {
                if (len >= 8) {
                        for (int n = (len / 8) - 1 ; n >= 0; n--)
                                data = (data << 8) + *(in+n);
@@ -322,15 +322,15 @@ static int restore_context(struct target *t)
        }
 
        for (i = 0; i < (x86_32->cache->num_regs); i++) {
-               x86_32->cache->reg_list[i].dirty = 0;
-               x86_32->cache->reg_list[i].valid = 0;
+               x86_32->cache->reg_list[i].dirty = false;
+               x86_32->cache->reg_list[i].valid = false;
        }
        return err;
 }
 
 /*
  * we keep reg_cache in sync with hardware at halt/resume time, we avoid
- * writing to real hardware here bacause pm_regs reflects the hardware
+ * writing to real hardware here because pm_regs reflects the hardware
  * while we are halted then reg_cache syncs with hw on resume
  * TODO - in order for "reg eip force" to work it assume get/set reads
  * and writes from hardware, may be other reasons also because generally
@@ -357,13 +357,13 @@ static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
        if (check_not_halted(t))
                return ERROR_TARGET_NOT_HALTED;
        buf_set_u32(reg->value, 0, 32, value);
-       reg->dirty = 1;
-       reg->valid = 1;
+       reg->dirty = true;
+       reg->valid = true;
        return ERROR_OK;
 }
 
 static const struct reg_arch_type lakemont_reg_type = {
-       /* these get called if reg_cache doesnt have a "valid" value
+       /* these get called if reg_cache doesn't have a "valid" value
         * of an individual reg eg "reg eip" but not for "reg" block
         */
        .get = lakemont_get_core_reg,
@@ -381,7 +381,7 @@ struct reg_cache *lakemont_build_reg_cache(struct target *t)
        struct reg_feature *feature;
        int i;
 
-       if (cache == NULL || reg_list == NULL || arch_info == NULL) {
+       if (!cache || !reg_list || !arch_info) {
                free(cache);
                free(reg_list);
                free(arch_info);
@@ -405,8 +405,8 @@ struct reg_cache *lakemont_build_reg_cache(struct target *t)
                reg_list[i].name = regs[i].name;
                reg_list[i].size = 32;
                reg_list[i].value = calloc(1, 4);
-               reg_list[i].dirty = 0;
-               reg_list[i].valid = 0;
+               reg_list[i].dirty = false;
+               reg_list[i].valid = false;
                reg_list[i].type = &lakemont_reg_type;
                reg_list[i].arch_info = &arch_info[i];
 
@@ -611,7 +611,7 @@ static int read_all_core_hw_regs(struct target *t)
        unsigned i;
        struct x86_32_common *x86_32 = target_to_x86_32(t);
        for (i = 0; i < (x86_32->cache->num_regs); i++) {
-               if (NOT_AVAIL_REG == regs[i].pm_idx)
+               if (regs[i].pm_idx == NOT_AVAIL_REG)
                        continue;
                err = read_hw_reg(t, regs[i].id, &regval, 1);
                if (err != ERROR_OK) {
@@ -630,7 +630,7 @@ static int write_all_core_hw_regs(struct target *t)
        unsigned i;
        struct x86_32_common *x86_32 = target_to_x86_32(t);
        for (i = 0; i < (x86_32->cache->num_regs); i++) {
-               if (NOT_AVAIL_REG == regs[i].pm_idx)
+               if (regs[i].pm_idx == NOT_AVAIL_REG)
                        continue;
                err = write_hw_reg(t, i, 0, 1);
                if (err != ERROR_OK) {
@@ -649,7 +649,7 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach
        struct x86_32_common *x86_32 = target_to_x86_32(t);
        struct lakemont_core_reg *arch_info;
        arch_info = x86_32->cache->reg_list[reg].arch_info;
-       x86_32->flush = 0; /* dont flush scans till we have a batch */
+       x86_32->flush = 0; /* don't flush scans till we have a batch */
        if (submit_reg_pir(t, reg) != ERROR_OK)
                return ERROR_FAIL;
        if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
@@ -667,8 +667,8 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach
        *regval = buf_get_u32(scan.out, 0, 32);
        if (cache) {
                buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
-               x86_32->cache->reg_list[reg].valid = 1;
-               x86_32->cache->reg_list[reg].dirty = 0;
+               x86_32->cache->reg_list[reg].valid = true;
+               x86_32->cache->reg_list[reg].dirty = false;
        }
        LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
                        x86_32->cache->reg_list[reg].name,
@@ -693,7 +693,7 @@ static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cach
                        arch_info->op,
                        regval);
 
-       x86_32->flush = 0; /* dont flush scans till we have a batch */
+       x86_32->flush = 0; /* don't flush scans till we have a batch */
        if (submit_reg_pir(t, reg) != ERROR_OK)
                return ERROR_FAIL;
        if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
@@ -709,8 +709,8 @@ static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cach
 
        /* we are writing from the cache so ensure we reset flags */
        if (cache) {
-               x86_32->cache->reg_list[reg].dirty = 0;
-               x86_32->cache->reg_list[reg].valid = 0;
+               x86_32->cache->reg_list[reg].dirty = false;
+               x86_32->cache->reg_list[reg].valid = false;
        }
        return ERROR_OK;
 }
@@ -940,15 +940,15 @@ int lakemont_poll(struct target *t)
                                 */
                                struct breakpoint *bp = NULL;
                                bp = breakpoint_find(t, eip-1);
-                               if (bp != NULL) {
+                               if (bp) {
                                        t->debug_reason = DBG_REASON_BREAKPOINT;
                                        if (bp->type == BKPT_SOFT) {
-                                               /* The EIP is now pointing the the next byte after the
+                                               /* The EIP is now pointing the next byte after the
                                                 * breakpoint instruction. This needs to be corrected.
                                                 */
                                                buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
-                                               x86_32->cache->reg_list[EIP].dirty = 1;
-                                               x86_32->cache->reg_list[EIP].valid = 1;
+                                               x86_32->cache->reg_list[EIP].dirty = true;
+                                               x86_32->cache->reg_list[EIP].valid = true;
                                                LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
                                        } else {
                                                /* it's not a hardware breakpoint (checked already in DR6 state)
@@ -1013,7 +1013,7 @@ int lakemont_resume(struct target *t, int current, target_addr_t address,
                /* running away for a software breakpoint needs some special handling */
                uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
                bp = breakpoint_find(t, eip);
-               if (bp != NULL /*&& bp->type == BKPT_SOFT*/) {
+               if (bp /*&& bp->type == BKPT_SOFT*/) {
                        /* the step will step over the breakpoint */
                        if (lakemont_step(t, 0, 0, 1) != ERROR_OK) {
                                LOG_ERROR("%s stepping over a software breakpoint at 0x%08" PRIx32 " "
@@ -1024,12 +1024,12 @@ int lakemont_resume(struct target *t, int current, target_addr_t address,
 
                /* if breakpoints are enabled, we need to redirect these into probe mode */
                struct breakpoint *activeswbp = t->breakpoints;
-               while (activeswbp != NULL && activeswbp->set == 0)
+               while (activeswbp && activeswbp->set == 0)
                        activeswbp = activeswbp->next;
                struct watchpoint *activehwbp = t->watchpoints;
-               while (activehwbp != NULL && activehwbp->set == 0)
+               while (activehwbp && activehwbp->set == 0)
                        activehwbp = activehwbp->next;
-               if (activeswbp != NULL || activehwbp != NULL)
+               if (activeswbp || activehwbp)
                        buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
                if (do_resume(t) != ERROR_OK)
                        return ERROR_FAIL;
@@ -1054,7 +1054,7 @@ int lakemont_step(struct target *t, int current,
        if (check_not_halted(t))
                return ERROR_TARGET_NOT_HALTED;
        bp = breakpoint_find(t, eip);
-       if (retval == ERROR_OK && bp != NULL/*&& bp->type == BKPT_SOFT*/) {
+       if (retval == ERROR_OK && bp/*&& bp->type == BKPT_SOFT*/) {
                /* TODO: This should only be done for software breakpoints.
                 * Stepping from hardware breakpoints should be possible with the resume flag
                 * Needs testing.
@@ -1070,7 +1070,8 @@ int lakemont_step(struct target *t, int current,
        LOG_DEBUG("EFLAGS [TF] [RF] bits set=0x%08" PRIx32 ", PMCR=0x%08" PRIx32 ", EIP=0x%08" PRIx32,
                        eflags, pmcr, eip);
 
-       tapstatus = get_tapstatus(t);
+       /* Returned value unused. Can this line be removed? */
+       get_tapstatus(t);
 
        t->debug_reason = DBG_REASON_SINGLESTEP;
        t->state = TARGET_DEBUG_RUNNING;
@@ -1105,7 +1106,7 @@ int lakemont_step(struct target *t, int current,
        /* try to re-apply the breakpoint, even of step failed
         * TODO: When a bp was set, we should try to stop the target - fix the return above
         */
-       if (bp != NULL/*&& bp->type == BKPT_SOFT*/) {
+       if (bp/*&& bp->type == BKPT_SOFT*/) {
                /* TODO: This should only be done for software breakpoints.
                 * Stepping from hardware breakpoints should be possible with the resume flag
                 * Needs testing.
@@ -1128,7 +1129,7 @@ static int lakemont_reset_break(struct target *t)
 
        /* prepare resetbreak setting the proper bits in CLTAPC_CPU_VPREQ */
        x86_32->curr_tap = jtag_tap_by_position(1);
-       if (x86_32->curr_tap == NULL) {
+       if (!x86_32->curr_tap) {
                x86_32->curr_tap = saved_tap;
                LOG_ERROR("%s could not select quark_x10xx.cltap", __func__);
                return ERROR_FAIL;
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