C99 printf() -Werror fixes
[openocd.git] / src / target / mips32.c
index 138a53553258828b5ae5b594697c4efb4791ee13..6c4bfb9a9d4670654b60e81d6414f5fa7c7ce81f 100644 (file)
@@ -116,7 +116,7 @@ int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
 {
        mips32_core_reg_t *mips32_reg = reg->arch_info;
        target_t *target = mips32_reg->target;
-       u32 value = buf_get_u32(buf, 0, 32);
+       uint32_t value = buf_get_u32(buf, 0, 32);
                
        if (target->state != TARGET_HALTED)
        {
@@ -132,7 +132,7 @@ int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
 
 int mips32_read_core_reg(struct target_s *target, int num)
 {
-       u32 reg_value;
+       uint32_t reg_value;
        mips32_core_reg_t *mips_core_reg;
        
        /* get pointers to arch-specific information */
@@ -152,7 +152,7 @@ int mips32_read_core_reg(struct target_s *target, int num)
 
 int mips32_write_core_reg(struct target_s *target, int num)
 {
-       u32 reg_value;
+       uint32_t reg_value;
        mips32_core_reg_t *mips_core_reg;
        
        /* get pointers to arch-specific information */
@@ -164,7 +164,7 @@ int mips32_write_core_reg(struct target_s *target, int num)
        reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
        mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
        mips32->core_regs[num] = reg_value;
-       LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
+       LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
        mips32->core_cache->reg_list[num].valid = 1;
        mips32->core_cache->reg_list[num].dirty = 0;
        
@@ -264,7 +264,7 @@ int mips32_arch_state(struct target_s *target)
                exit(-1);
        }
        
-       LOG_USER("target halted due to %s, pc: 0x%8.8x",
+       LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
                Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
                buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
        
@@ -336,7 +336,7 @@ int mips32_register_commands(struct command_context_s *cmd_ctx)
        return ERROR_OK;
 }
 
-int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
+int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
        /*TODO*/
        return ERROR_OK;
@@ -366,7 +366,7 @@ int mips32_configure_break_unit(struct target_s *target)
        /* get pointers to arch-specific information */
        mips32_common_t *mips32 = target->arch_info;
        int retval;
-       u32 dcr, bpinfo;
+       uint32_t dcr, bpinfo;
        int i;
        
        if (mips32->bp_scanned)
@@ -414,7 +414,7 @@ int mips32_configure_break_unit(struct target_s *target)
                        return retval;
        }
        
-       LOG_DEBUG("DCR 0x%x numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
+       LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
        
        mips32->bp_scanned = 1;
        
@@ -425,7 +425,7 @@ int mips32_enable_interrupts(struct target_s *target, int enable)
 {
        int retval;
        int update = 0;
-       u32 dcr;
+       uint32_t dcr;
        
        /* read debug control register */
        if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)

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