return ERROR_OK;
}
-static int mips32_read_core_reg(struct target *target, int num)
+static int mips32_read_core_reg(struct target *target, unsigned int num)
{
uint32_t reg_value;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
- if ((num < 0) || (num >= MIPS32NUMCOREREGS))
+ if (num >= MIPS32NUMCOREREGS)
return ERROR_COMMAND_SYNTAX_ERROR;
reg_value = mips32->core_regs[num];
return ERROR_OK;
}
-static int mips32_write_core_reg(struct target *target, int num)
+static int mips32_write_core_reg(struct target *target, unsigned int num)
{
uint32_t reg_value;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
- if ((num < 0) || (num >= MIPS32NUMCOREREGS))
+ if (num >= MIPS32NUMCOREREGS)
return ERROR_COMMAND_SYNTAX_ERROR;
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
- int i;
+ unsigned int i;
/* include floating point registers */
*reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
int mips32_save_context(struct target *target)
{
- int i;
+ unsigned int i;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
int mips32_restore_context(struct target *target)
{
- int i;
+ unsigned int i;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
mips32->common_magic = MIPS32_COMMON_MAGIC;
mips32->fast_data_area = NULL;
- /* has breakpoint/watchpint unit been scanned */
+ /* has breakpoint/watchpoint unit been scanned */
mips32->bp_scanned = 0;
mips32->data_break_list = NULL;
enum mips32_isa_mode isa_mode = mips32->isa_mode;
uint32_t context[MIPS32NUMCOREREGS];
- int i;
int retval = ERROR_OK;
LOG_DEBUG("Running algorithm");
}
/* refresh core register cache */
- for (i = 0; i < MIPS32NUMCOREREGS; i++) {
+ for (unsigned int i = 0; i < MIPS32NUMCOREREGS; i++) {
if (!mips32->core_cache->reg_list[i].valid)
mips32->read_core_reg(target, i);
context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
}
- for (i = 0; i < num_mem_params; i++) {
+ for (int i = 0; i < num_mem_params; i++) {
retval = target_write_buffer(target, mem_params[i].address,
mem_params[i].size, mem_params[i].value);
if (retval != ERROR_OK)
return retval;
}
- for (i = 0; i < num_reg_params; i++) {
+ for (int i = 0; i < num_reg_params; i++) {
struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
if (!reg) {
if (retval != ERROR_OK)
return retval;
- for (i = 0; i < num_mem_params; i++) {
+ for (int i = 0; i < num_mem_params; i++) {
if (mem_params[i].direction != PARAM_OUT) {
retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size,
mem_params[i].value);
}
}
- for (i = 0; i < num_reg_params; i++) {
+ for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction != PARAM_OUT) {
struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
if (!reg) {
}
/* restore everything we saved before */
- for (i = 0; i < MIPS32NUMCOREREGS; i++) {
+ for (unsigned int i = 0; i < MIPS32NUMCOREREGS; i++) {
uint32_t regvalue;
regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
if (regvalue != context[i]) {
if (retval != ERROR_OK)
return retval;
- /* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR.
- * Since these DCR bits should be reserved on EJTAG 2.0, we can
- * just remap them. */
+ /* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR. */
if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
+ ejtag_info->debug_caps = dcr & EJTAG_DCR_ENM;
if (!(ejtag_info->impcode & EJTAG_V20_IMP_NOIB))
- dcr |= EJTAG_DCR_IB;
+ ejtag_info->debug_caps |= EJTAG_DCR_IB;
if (!(ejtag_info->impcode & EJTAG_V20_IMP_NODB))
- dcr |= EJTAG_DCR_DB;
- }
+ ejtag_info->debug_caps |= EJTAG_DCR_DB;
+ } else
+ /* keep debug caps for later use */
+ ejtag_info->debug_caps = dcr & (EJTAG_DCR_ENM
+ | EJTAG_DCR_IB | EJTAG_DCR_DB);
+
- if (dcr & EJTAG_DCR_IB) {
+ if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
retval = mips32_configure_ibs(target);
if (retval != ERROR_OK)
return retval;
}
- if (dcr & EJTAG_DCR_DB) {
+ if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
retval = mips32_configure_dbs(target);
if (retval != ERROR_OK)
return retval;
}
/* check if target endianness settings matches debug control register */
- if (((dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN)) ||
- (!(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN)))
+ if (((ejtag_info->debug_caps & EJTAG_DCR_ENM)
+ && (target->endianness == TARGET_LITTLE_ENDIAN)) ||
+ (!(ejtag_info->debug_caps & EJTAG_DCR_ENM)
+ && (target->endianness == TARGET_BIG_ENDIAN)))
LOG_WARNING("DCR endianness settings does not match target settings");
LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,