* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "algorithm.h"
#include "register.h"
-static char *mips32_core_reg_list[] = {
- "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
- "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
- "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
- "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
- "status", "lo", "hi", "badvaddr", "cause", "pc"
-};
-
static const char *mips_isa_strings[] = {
"MIPS32", "MIPS16e"
};
-static struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = {
- {0, NULL, NULL},
- {1, NULL, NULL},
- {2, NULL, NULL},
- {3, NULL, NULL},
- {4, NULL, NULL},
- {5, NULL, NULL},
- {6, NULL, NULL},
- {7, NULL, NULL},
- {8, NULL, NULL},
- {9, NULL, NULL},
- {10, NULL, NULL},
- {11, NULL, NULL},
- {12, NULL, NULL},
- {13, NULL, NULL},
- {14, NULL, NULL},
- {15, NULL, NULL},
- {16, NULL, NULL},
- {17, NULL, NULL},
- {18, NULL, NULL},
- {19, NULL, NULL},
- {20, NULL, NULL},
- {21, NULL, NULL},
- {22, NULL, NULL},
- {23, NULL, NULL},
- {24, NULL, NULL},
- {25, NULL, NULL},
- {26, NULL, NULL},
- {27, NULL, NULL},
- {28, NULL, NULL},
- {29, NULL, NULL},
- {30, NULL, NULL},
- {31, NULL, NULL},
-
- {32, NULL, NULL},
- {33, NULL, NULL},
- {34, NULL, NULL},
- {35, NULL, NULL},
- {36, NULL, NULL},
- {37, NULL, NULL},
+static const struct {
+ unsigned id;
+ const char *name;
+} mips32_regs[MIPS32NUMCOREREGS] = {
+ { 0, "zero", },
+ { 1, "at", },
+ { 2, "v0", },
+ { 3, "v1", },
+ { 4, "a0", },
+ { 5, "a1", },
+ { 6, "a2", },
+ { 7, "a3", },
+ { 8, "t0", },
+ { 9, "t1", },
+ { 10, "t2", },
+ { 11, "t3", },
+ { 12, "t4", },
+ { 13, "t5", },
+ { 14, "t6", },
+ { 15, "t7", },
+ { 16, "s0", },
+ { 17, "s1", },
+ { 18, "s2", },
+ { 19, "s3", },
+ { 20, "s4", },
+ { 21, "s5", },
+ { 22, "s6", },
+ { 23, "s7", },
+ { 24, "t8", },
+ { 25, "t9", },
+ { 26, "k0", },
+ { 27, "k1", },
+ { 28, "gp", },
+ { 29, "sp", },
+ { 30, "fp", },
+ { 31, "ra", },
+
+ { 32, "status", },
+ { 33, "lo", },
+ { 34, "hi", },
+ { 35, "badvaddr", },
+ { 36, "cause", },
+ { 37, "pc" },
};
/* number of mips dummy fp regs fp0 - fp31 + fsr and fir
return ERROR_OK;
}
-int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
+int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
+ int *reg_list_size, enum target_register_class reg_class)
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
int num_regs = MIPS32NUMCOREREGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
+ struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
int i;
mips32->core_cache = cache;
for (i = 0; i < num_regs; i++) {
- arch_info[i] = mips32_core_reg_list_arch_info[i];
+ arch_info[i].num = mips32_regs[i].id;
arch_info[i].target = target;
arch_info[i].mips32_common = mips32;
- reg_list[i].name = mips32_core_reg_list[i];
+
+ reg_list[i].name = mips32_regs[i].name;
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
mips32->read_core_reg = mips32_read_core_reg;
mips32->write_core_reg = mips32_write_core_reg;
+ mips32->ejtag_info.scan_delay = 2000000; /* Initial default value */
+ mips32->ejtag_info.mode = 0; /* Initial default value */
+
return ERROR_OK;
}
return ERROR_OK;
}
+static int mips32_configure_ibs(struct target *target)
+{
+ struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ int retval, i;
+ uint32_t bpinfo;
+
+ /* get number of inst breakpoints */
+ retval = target_read_u32(target, ejtag_info->ejtag_ibs_addr, &bpinfo);
+ if (retval != ERROR_OK)
+ return retval;
+
+ mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
+ mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
+ mips32->inst_break_list = calloc(mips32->num_inst_bpoints,
+ sizeof(struct mips32_comparator));
+
+ for (i = 0; i < mips32->num_inst_bpoints; i++)
+ mips32->inst_break_list[i].reg_address =
+ ejtag_info->ejtag_iba0_addr +
+ (ejtag_info->ejtag_iba_step_size * i);
+
+ /* clear IBIS reg */
+ retval = target_write_u32(target, ejtag_info->ejtag_ibs_addr, 0);
+ return retval;
+}
+
+static int mips32_configure_dbs(struct target *target)
+{
+ struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ int retval, i;
+ uint32_t bpinfo;
+
+ /* get number of data breakpoints */
+ retval = target_read_u32(target, ejtag_info->ejtag_dbs_addr, &bpinfo);
+ if (retval != ERROR_OK)
+ return retval;
+
+ mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
+ mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
+ mips32->data_break_list = calloc(mips32->num_data_bpoints,
+ sizeof(struct mips32_comparator));
+
+ for (i = 0; i < mips32->num_data_bpoints; i++)
+ mips32->data_break_list[i].reg_address =
+ ejtag_info->ejtag_dba0_addr +
+ (ejtag_info->ejtag_dba_step_size * i);
+
+ /* clear DBIS reg */
+ retval = target_write_u32(target, ejtag_info->ejtag_dbs_addr, 0);
+ return retval;
+}
+
int mips32_configure_break_unit(struct target *target)
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
int retval;
- uint32_t dcr, bpinfo;
- int i;
+ uint32_t dcr;
if (mips32->bp_scanned)
return ERROR_OK;
if (retval != ERROR_OK)
return retval;
- if (dcr & EJTAG_DCR_IB) {
- /* get number of inst breakpoints */
- retval = target_read_u32(target, EJTAG_IBS, &bpinfo);
- if (retval != ERROR_OK)
- return retval;
-
- mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
- mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
- mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
- for (i = 0; i < mips32->num_inst_bpoints; i++)
- mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
+ /* EJTAG 2.0 does not specify EJTAG_DCR_IB and EJTAG_DCR_DB bits,
+ * assume IB and DB registers are always present. */
+ if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
+ dcr |= EJTAG_DCR_IB | EJTAG_DCR_DB;
- /* clear IBIS reg */
- retval = target_write_u32(target, EJTAG_IBS, 0);
+ if (dcr & EJTAG_DCR_IB) {
+ retval = mips32_configure_ibs(target);
if (retval != ERROR_OK)
return retval;
}
if (dcr & EJTAG_DCR_DB) {
- /* get number of data breakpoints */
- retval = target_read_u32(target, EJTAG_DBS, &bpinfo);
- if (retval != ERROR_OK)
- return retval;
-
- mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
- mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
- mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
- for (i = 0; i < mips32->num_data_bpoints; i++)
- mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
-
- /* clear DBIS reg */
- retval = target_write_u32(target, EJTAG_DBS, 0);
+ retval = mips32_configure_dbs(target);
if (retval != ERROR_OK)
return retval;
}
struct working_area *crc_algorithm;
struct reg_param reg_params[2];
struct mips32_algorithm mips32_info;
- int retval;
- uint32_t i;
- /* see contib/loaders/checksum/mips32.s for src */
+ /* see contrib/loaders/checksum/mips32.s for src */
static const uint32_t mips_crc_code[] = {
0x248C0000, /* addiu $t4, $a0, 0 */
if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- /* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++)
- target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]);
+ /* convert mips crc code into a buffer in target endianness */
+ uint8_t mips_crc_code_8[sizeof(mips_crc_code)];
+ target_buffer_set_u32_array(target, mips_crc_code_8,
+ ARRAY_SIZE(mips_crc_code), mips_crc_code);
+
+ target_write_buffer(target, crc_algorithm->address, sizeof(mips_crc_code), mips_crc_code_8);
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
int timeout = 20000 * (1 + (count / (1024 * 1024)));
- retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
- crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout,
+ int retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
+ crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code) - 4), timeout,
&mips32_info);
- if (retval != ERROR_OK) {
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- target_free_working_area(target, crc_algorithm);
- return 0;
- }
- *checksum = buf_get_u32(reg_params[0].value, 0, 32);
+ if (retval == ERROR_OK)
+ *checksum = buf_get_u32(reg_params[0].value, 0, 32);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
target_free_working_area(target, crc_algorithm);
- return ERROR_OK;
+ return retval;
}
/** Checks whether a memory region is zeroed. */
struct working_area *erase_check_algorithm;
struct reg_param reg_params[3];
struct mips32_algorithm mips32_info;
- int retval;
- uint32_t i;
static const uint32_t erase_check_code[] = {
/* nbyte: */
if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- /* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) {
- target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t),
- erase_check_code[i]);
- }
+ /* convert erase check code into a buffer in target endianness */
+ uint8_t erase_check_code_8[sizeof(erase_check_code)];
+ target_buffer_set_u32_array(target, erase_check_code_8,
+ ARRAY_SIZE(erase_check_code), erase_check_code);
+
+ target_write_buffer(target, erase_check_algorithm->address, sizeof(erase_check_code), erase_check_code_8);
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
init_reg_param(®_params[2], "a2", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
- retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+ int retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
erase_check_algorithm->address,
- erase_check_algorithm->address + (sizeof(erase_check_code)-2),
+ erase_check_algorithm->address + (sizeof(erase_check_code) - 4),
10000, &mips32_info);
- if (retval != ERROR_OK) {
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- destroy_reg_param(®_params[2]);
- target_free_working_area(target, erase_check_algorithm);
- return 0;
- }
- *blank = buf_get_u32(reg_params[2].value, 0, 32);
+ if (retval == ERROR_OK)
+ *blank = buf_get_u32(reg_params[2].value, 0, 32);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
target_free_working_area(target, erase_check_algorithm);
- return ERROR_OK;
+ return retval;
}
static int mips32_verify_pointer(struct command_context *cmd_ctx,
cp0_reg);
return ERROR_OK;
}
- retval = jtag_execute_queue();
- if (retval != ERROR_OK)
- return retval;
-
command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
cp0_reg, cp0_sel, value);
+
} else if (CMD_ARGC == 3) {
uint32_t value;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
return ERROR_OK;
}
+COMMAND_HANDLER(mips32_handle_scan_delay_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
+ else if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
+ if (ejtag_info->scan_delay >= 2000000) {
+ ejtag_info->mode = 0;
+ command_print(CMD_CTX, "running in legacy mode");
+ } else {
+ ejtag_info->mode = 1;
+ command_print(CMD_CTX, "running in fast queued mode");
+ }
+
+ return ERROR_OK;
+}
+
static const struct command_registration mips32_exec_command_handlers[] = {
{
.name = "cp0",
.mode = COMMAND_EXEC,
.usage = "regnum select [value]",
.help = "display/modify cp0 register",
+ },
+ {
+ .name = "scan_delay",
+ .handler = mips32_handle_scan_delay_command,
+ .mode = COMMAND_ANY,
+ .help = "display/set scan delay in nano seconds",
+ .usage = "[value]",
},
COMMAND_REGISTRATION_DONE
};
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