jtag newtap change & huge manual update

[openocd.git] / src / target / mips32.h

diff --git a/src/target/mips32.h b/src/target/mips32.h
index aeed1a605e47e2386a810d6e848b8a2d0179c6a1..02f88b0a9c0a1d669438e49fca29aed3b9dd84df 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -37,6 +37,14 @@ enum
        MIPS32NUMCOREREGS
 };
 
+typedef struct mips32_comparator_s
+{
+       int used;
+       //int type;
+       u32 bp_value;
+       u32 reg_address;
+} mips32_comparator_t;
+
 typedef struct mips32_common_s
 {
        int common_magic;
@@ -45,6 +53,14 @@ typedef struct mips32_common_s
        mips_ejtag_t ejtag_info;
        u32 core_regs[MIPS32NUMCOREREGS];
        
+       int bp_scanned;
+       int num_inst_bpoints;
+       int num_data_bpoints;
+       int num_inst_bpoints_avail;
+       int num_data_bpoints_avail;
+       mips32_comparator_t *inst_break_list;
+       mips32_comparator_t *data_break_list;
+       
        /* register cache to processor synchronization */
        int (*read_core_reg)(struct target_s *target, int num);
        int (*write_core_reg)(struct target_s *target, int num);
@@ -66,7 +82,9 @@ typedef struct mips32_core_reg_s
 #define MIPS32_OP_LBU  0x24
 #define MIPS32_OP_LHU  0x25
 #define MIPS32_OP_MFHI 0x10
+#define MIPS32_OP_MTHI 0x11
 #define MIPS32_OP_MFLO 0x12
+#define MIPS32_OP_MTLO 0x13
 #define MIPS32_OP_SB   0x28
 #define MIPS32_OP_SH   0x29
 #define MIPS32_OP_SW   0x2B
@@ -90,8 +108,10 @@ typedef struct mips32_core_reg_s
 #define MIPS32_LHU(reg, off, base)     MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
 #define MIPS32_LUI(reg, val)           MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
 #define MIPS32_LW(reg, off, base)      MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
-#define MIPS32_LO(reg)                         MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
-#define MIPS32_HI(reg)                         MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
+#define MIPS32_MFLO(reg)                       MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
+#define MIPS32_MFHI(reg)                       MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
+#define MIPS32_MTLO(reg)                       MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTLO)
+#define MIPS32_MTHI(reg)                       MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTHI)
 #define MIPS32_ORI(src, tar, val)      MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
 #define MIPS32_SB(reg, off, base)      MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
 #define MIPS32_SH(reg, off, base)      MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
@@ -99,11 +119,13 @@ typedef struct mips32_core_reg_s
 #define MIPS32_DRET                                    0x4200001F
 
 extern int mips32_arch_state(struct target_s *target);
-extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, char *variant);
+extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap, const char *variant);
 extern int mips32_restore_context(target_t *target);
 extern int mips32_save_context(target_t *target);
 extern reg_cache_t *mips32_build_reg_cache(target_t *target);
 extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+extern int mips32_configure_break_unit(struct target_s *target);
+extern int mips32_examine(struct target_s *target);
 
 extern int mips32_register_commands(struct command_context_s *cmd_ctx);
 extern int mips32_invalidate_core_regs(target_t *target);