struct mips32_comparator *data_break_list;
/* register cache to processor synchronization */
- int (*read_core_reg)(struct target *target, int num);
- int (*write_core_reg)(struct target *target, int num);
+ int (*read_core_reg)(struct target *target, unsigned int num);
+ int (*write_core_reg)(struct target *target, unsigned int num);
};
static inline struct mips32_common *
#define MIPS32_OP_AND 0x24
#define MIPS32_OP_CACHE 0x2F
#define MIPS32_OP_COP0 0x10
+#define MIPS32_OP_J 0x02
#define MIPS32_OP_JR 0x08
#define MIPS32_OP_LUI 0x0F
#define MIPS32_OP_LW 0x23
#define MIPS32_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
#define MIPS32_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
#define MIPS32_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
+#define MIPS32_J(tar) MIPS32_J_INST(MIPS32_OP_J, tar)
#define MIPS32_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
#define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
#define MIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
#define MIPS32_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */
/**
- * Cache operations definietions
+ * Cache operations definitions
* Operation field is 5 bits long :
* 1) bits 1..0 hold cache type
* 2) bits 4..2 hold operation code
int mips32_register_commands(struct command_context *cmd_ctx);
int mips32_get_gdb_reg_list(struct target *target,
- struct reg **reg_list[], int *reg_list_size);
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class);
int mips32_checksum_memory(struct target *target, uint32_t address,
uint32_t count, uint32_t *checksum);
int mips32_blank_check_memory(struct target *target,