-/**
- * \b mips32_pracc_clean_invalidate_cache
- *
- * Writeback D$ and Invalidate I$
- * so that the instructions written can be visible to CPU
- */
-static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info,
- uint32_t start_addr, uint32_t end_addr)
-{
- static const uint32_t code[] = {
- /* start: */
- MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
- MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
- MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
- MIPS32_SW(8, 0, 15), /* sw $8,($15) */
- MIPS32_SW(9, 0, 15), /* sw $9,($15) */
- MIPS32_SW(10, 0, 15), /* sw $10,($15) */
- MIPS32_SW(11, 0, 15), /* sw $11,($15) */
-
- MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
- MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)),
- MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */
- MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */
- MIPS32_LW(11, 8, 8), /* Load write clsiz to $11 */
-
- /* cache_loop: */
- MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 : $8 <- $10 < $9 ? */
- MIPS32_BGTZ(8, 6), /* bgtz $8, end */
- MIPS32_NOP,
-
- MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK, 0, 9), /* cache Hit_Writeback_D, 0($9) */
- MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE, 0, 9), /* cache Hit_Invalidate_I, 0($9) */
-
- MIPS32_ADDU(9, 9, 11), /* $9 += $11 */
-
- MIPS32_B(NEG16(7)), /* b cache_loop */
- MIPS32_NOP,
- /* end: */
- MIPS32_LW(11, 0, 15), /* lw $11,($15) */
- MIPS32_LW(10, 0, 15), /* lw $10,($15) */
- MIPS32_LW(9, 0, 15), /* lw $9,($15) */
- MIPS32_LW(8, 0, 15), /* lw $8,($15) */
- MIPS32_B(NEG16(25)), /* b start */
- MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
- };