* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
/*
* The original code contained NOPs. I have removed these and moved
* the branches.
*
- * I also moved the PRACC_STACK to 0xFF204000. This allows
- * the use of 16 bits offsets to get pointers to the input
- * and output area relative to the stack. Note that the stack
- * isn't really a stack (the stack pointer is not 'moving')
- * but a FIFO simulated in software.
- *
* These changes result in a 35% speed increase when programming an
* external flash.
*
#include "mips32.h"
#include "mips32_pracc.h"
-struct mips32_pracc_context {
- uint32_t *local_iparam;
- int num_iparam;
- uint32_t *local_oparam;
- int num_oparam;
- const uint32_t *code;
- int code_len;
- uint32_t stack[32];
- int stack_offset;
- struct mips_ejtag *ejtag_info;
-};
-
-static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info,
- uint32_t start_addr, uint32_t end_addr);
-static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info,
- uint32_t start_addr, uint32_t end_addr);
-
-static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl)
+static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info)
{
- uint32_t ejtag_ctrl;
- long long then = timeval_ms();
- int timeout;
- int retval;
+ int64_t then = timeval_ms();
/* wait for the PrAcc to become "1" */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
while (1) {
- ejtag_ctrl = ejtag_info->ejtag_ctrl;
- retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ ejtag_info->pa_ctrl = ejtag_info->ejtag_ctrl;
+ int retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_info->pa_ctrl);
if (retval != ERROR_OK)
return retval;
- if (ejtag_ctrl & EJTAG_CTRL_PRACC)
+ if (ejtag_info->pa_ctrl & EJTAG_CTRL_PRACC)
break;
- timeout = timeval_ms() - then;
+ int64_t timeout = timeval_ms() - then;
if (timeout > 1000) {
LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
return ERROR_JTAG_DEVICE_ERROR;
}
}
- *ctrl = ejtag_ctrl;
return ERROR_OK;
}
-static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t address)
+/* Shift in control and address for a new processor access, save them in ejtag_info */
+static int mips32_pracc_read_ctrl_addr(struct mips_ejtag *ejtag_info)
{
- struct mips_ejtag *ejtag_info = ctx->ejtag_info;
- int offset;
- uint32_t ejtag_ctrl, data;
-
- if ((address >= MIPS32_PRACC_PARAM_IN)
- && (address < MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) {
- offset = (address - MIPS32_PRACC_PARAM_IN) / 4;
- data = ctx->local_iparam[offset];
- } else if ((address >= MIPS32_PRACC_PARAM_OUT)
- && (address < MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) {
- offset = (address - MIPS32_PRACC_PARAM_OUT) / 4;
- data = ctx->local_oparam[offset];
- } else if ((address >= MIPS32_PRACC_TEXT)
- && (address < MIPS32_PRACC_TEXT + ctx->code_len * 4)) {
- offset = (address - MIPS32_PRACC_TEXT) / 4;
- data = ctx->code[offset];
- } else if (address == MIPS32_PRACC_STACK) {
- if (ctx->stack_offset <= 0) {
- LOG_ERROR("Error: Pracc stack out of bounds");
- return ERROR_JTAG_DEVICE_ERROR;
- }
- /* save to our debug stack */
- data = ctx->stack[--ctx->stack_offset];
- } else {
- /* TODO: send JMP 0xFF200000 instruction. Hopefully processor jump back
- * to start of debug vector */
-
- LOG_ERROR("Error reading unexpected address 0x%8.8" PRIx32 "", address);
- return ERROR_JTAG_DEVICE_ERROR;
- }
+ int retval = wait_for_pracc_rw(ejtag_info);
+ if (retval != ERROR_OK)
+ return retval;
- /* Send the data out */
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
- mips_ejtag_drscan_32_out(ctx->ejtag_info, data);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
- /* Clear the access pending bit (let the processor eat!) */
- ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
- mips_ejtag_drscan_32_out(ctx->ejtag_info, ejtag_ctrl);
+ ejtag_info->pa_addr = 0;
+ return mips_ejtag_drscan_32(ejtag_info, &ejtag_info->pa_addr);
+}
- return jtag_execute_queue();
+/* Finish processor access */
+static void mips32_pracc_finish(struct mips_ejtag *ejtag_info)
+{
+ uint32_t ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
+ mips_ejtag_drscan_32_out(ejtag_info, ctrl);
}
-static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t address)
+int mips32_pracc_clean_text_jump(struct mips_ejtag *ejtag_info)
{
- uint32_t ejtag_ctrl, data;
- int offset;
- struct mips_ejtag *ejtag_info = ctx->ejtag_info;
- int retval;
+ uint32_t jt_code = MIPS32_J((0x0FFFFFFF & MIPS32_PRACC_TEXT) >> 2);
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
- retval = mips_ejtag_drscan_32(ctx->ejtag_info, &data);
- if (retval != ERROR_OK)
- return retval;
+ /* do 3 0/nops to clean pipeline before a jump to pracc text, NOP in delay slot */
+ for (int i = 0; i != 5; i++) {
+ /* Wait for pracc */
+ int retval = wait_for_pracc_rw(ejtag_info);
+ if (retval != ERROR_OK)
+ return retval;
- /* Clear access pending bit */
- ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
- mips_ejtag_drscan_32_out(ctx->ejtag_info, ejtag_ctrl);
+ /* Data or instruction out */
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
+ uint32_t data = (i == 3) ? jt_code : MIPS32_NOP;
+ mips_ejtag_drscan_32_out(ejtag_info, data);
- retval = jtag_execute_queue();
- if (retval != ERROR_OK)
- return retval;
+ /* finish pa */
+ mips32_pracc_finish(ejtag_info);
+ }
- if ((address >= MIPS32_PRACC_PARAM_OUT)
- && (address < MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) {
- offset = (address - MIPS32_PRACC_PARAM_OUT) / 4;
- ctx->local_oparam[offset] = data;
- } else if (address == MIPS32_PRACC_STACK) {
- if (ctx->stack_offset >= 32) {
- LOG_ERROR("Error: Pracc stack out of bounds");
- return ERROR_JTAG_DEVICE_ERROR;
- }
- /* save data onto our stack */
- ctx->stack[ctx->stack_offset++] = data;
- } else {
- LOG_ERROR("Error writing unexpected address 0x%8.8" PRIx32 "", address);
- return ERROR_JTAG_DEVICE_ERROR;
+ if (ejtag_info->mode != 0) /* async mode support only for MIPS ... */
+ return ERROR_OK;
+
+ for (int i = 0; i != 2; i++) {
+ int retval = mips32_pracc_read_ctrl_addr(ejtag_info);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT) { /* LEXRA/BMIPS ?, shift out another NOP, max 2 */
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
+ mips_ejtag_drscan_32_out(ejtag_info, MIPS32_NOP);
+ mips32_pracc_finish(ejtag_info);
+ } else
+ break;
}
return ERROR_OK;
}
-int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code,
- int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle)
+int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *param_out)
{
- uint32_t ejtag_ctrl;
- uint32_t address;
- struct mips32_pracc_context ctx;
+ int code_count = 0;
+ int store_pending = 0; /* increases with every store instruction at dmseg, decreases with every store pa */
+ uint32_t max_store_addr = 0; /* for store pa address testing */
+ bool restart = 0; /* restarting control */
+ int restart_count = 0;
+ uint32_t instr = 0;
+ bool final_check = 0; /* set to 1 if in final checks after function code shifted out */
+ bool pass = 0; /* to check the pass through pracc text after function code sent */
int retval;
- int pass = 0;
-
- ctx.local_iparam = param_in;
- ctx.local_oparam = param_out;
- ctx.num_iparam = num_param_in;
- ctx.num_oparam = num_param_out;
- ctx.code = code;
- ctx.code_len = code_len;
- ctx.ejtag_info = ejtag_info;
- ctx.stack_offset = 0;
while (1) {
- retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
- if (retval != ERROR_OK)
- return retval;
+ if (restart) {
+ if (restart_count < 3) { /* max 3 restarts allowed */
+ retval = mips32_pracc_clean_text_jump(ejtag_info);
+ if (retval != ERROR_OK)
+ return retval;
+ } else
+ return ERROR_JTAG_DEVICE_ERROR;
+ restart_count++;
+ restart = 0;
+ code_count = 0;
+ LOG_DEBUG("restarting code");
+ }
- address = 0;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
- retval = mips_ejtag_drscan_32(ejtag_info, &address);
+ retval = mips32_pracc_read_ctrl_addr(ejtag_info); /* update current pa info: control and address */
if (retval != ERROR_OK)
return retval;
- /* Check for read or write */
- if (ejtag_ctrl & EJTAG_CTRL_PRNW) {
- retval = mips32_pracc_exec_write(&ctx, address);
- if (retval != ERROR_OK)
- return retval;
- } else {
- /* Check to see if its reading at the debug vector. The first pass through
- * the module is always read at the vector, so the first one we allow. When
- * the second read from the vector occurs we are done and just exit. */
- if ((address == MIPS32_PRACC_TEXT) && (pass++))
- break;
+ /* Check for read or write access */
+ if (ejtag_info->pa_ctrl & EJTAG_CTRL_PRNW) { /* write/store access */
+ /* Check for pending store from a previous store instruction at dmseg */
+ if (store_pending == 0) {
+ LOG_DEBUG("unexpected write at address %" PRIx32, ejtag_info->pa_addr);
+ if (code_count < 2) { /* allow for restart */
+ restart = 1;
+ continue;
+ } else
+ return ERROR_JTAG_DEVICE_ERROR;
+ } else {
+ /* check address */
+ if (ejtag_info->pa_addr < MIPS32_PRACC_PARAM_OUT || ejtag_info->pa_addr > max_store_addr) {
- retval = mips32_pracc_exec_read(&ctx, address);
+ LOG_DEBUG("writing at unexpected address %" PRIx32, ejtag_info->pa_addr);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+ /* read data */
+ uint32_t data = 0;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
+ retval = mips_ejtag_drscan_32(ejtag_info, &data);
if (retval != ERROR_OK)
return retval;
+
+ /* store data at param out, address based offset */
+ param_out[(ejtag_info->pa_addr - MIPS32_PRACC_PARAM_OUT) / 4] = data;
+ store_pending--;
+
+ } else { /* read/fetch access */
+ if (!final_check) { /* executing function code */
+ /* check address */
+ if (ejtag_info->pa_addr != (MIPS32_PRACC_TEXT + code_count * 4)) {
+ LOG_DEBUG("reading at unexpected address %" PRIx32 ", expected %x",
+ ejtag_info->pa_addr, MIPS32_PRACC_TEXT + code_count * 4);
+
+ /* restart code execution only in some cases */
+ if (code_count == 1 && ejtag_info->pa_addr == MIPS32_PRACC_TEXT && restart_count == 0) {
+ LOG_DEBUG("restarting, without clean jump");
+ restart_count++;
+ code_count = 0;
+ continue;
+ } else if (code_count < 2) {
+ restart = 1;
+ continue;
+ }
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ /* check for store instruction at dmseg */
+ uint32_t store_addr = ctx->pracc_list[code_count].addr;
+ if (store_addr != 0) {
+ if (store_addr > max_store_addr)
+ max_store_addr = store_addr;
+ store_pending++;
+ }
+
+ instr = ctx->pracc_list[code_count++].instr;
+ if (code_count == ctx->code_count) /* last instruction, start final check */
+ final_check = 1;
+
+ } else { /* final check after function code shifted out */
+ /* check address */
+ if (ejtag_info->pa_addr == MIPS32_PRACC_TEXT) {
+ if (!pass) { /* first pass through pracc text */
+ if (store_pending == 0) /* done, normal exit */
+ return ERROR_OK;
+ pass = 1; /* pracc text passed */
+ code_count = 0; /* restart code count */
+ } else {
+ LOG_DEBUG("unexpected second pass through pracc text");
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ } else {
+ if (ejtag_info->pa_addr != (MIPS32_PRACC_TEXT + code_count * 4)) {
+ LOG_DEBUG("unexpected read address in final check: %" PRIx32 ", expected: %x",
+ ejtag_info->pa_addr, MIPS32_PRACC_TEXT + code_count * 4);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+ if (!pass) {
+ if ((code_count - ctx->code_count) > 1) { /* allow max 2 instruction delay slot */
+ LOG_DEBUG("failed to jump back to pracc text");
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ } else
+ if (code_count > 10) { /* enough, abandone */
+ LOG_DEBUG("execution abandoned, store pending: %d", store_pending);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ instr = MIPS32_NOP; /* shift out NOPs instructions */
+ code_count++;
+ }
+
+ /* Send instruction out */
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
+ mips_ejtag_drscan_32_out(ejtag_info, instr);
}
+ /* finish processor access, let the processor eat! */
+ mips32_pracc_finish(ejtag_info);
- if (cycle == 0)
- break;
+ if (instr == MIPS32_DRET) /* after leaving debug mode nothing to do */
+ return jtag_execute_queue();
+
+ if (store_pending == 0 && pass) { /* store access done, but after passing pracc text */
+ LOG_DEBUG("warning: store access pass pracc text");
+ return ERROR_OK;
+ }
}
+}
- /* stack sanity check */
- if (ctx.stack_offset != 0)
- LOG_DEBUG("Pracc Stack not zero");
+inline void pracc_queue_init(struct pracc_queue_info *ctx)
+{
+ ctx->retval = ERROR_OK;
+ ctx->code_count = 0;
+ ctx->store_count = 0;
+ ctx->max_code = 0;
+ ctx->pracc_list = NULL;
+}
- return ERROR_OK;
+void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)
+{
+ if (ctx->retval != ERROR_OK) /* On previous out of memory, return */
+ return;
+ if (ctx->code_count == ctx->max_code) {
+ void *p = realloc(ctx->pracc_list, sizeof(pa_list) * (ctx->max_code + PRACC_BLOCK));
+ if (p) {
+ ctx->max_code += PRACC_BLOCK;
+ ctx->pracc_list = p;
+ } else {
+ ctx->retval = ERROR_FAIL; /* Out of memory */
+ return;
+ }
+ }
+ ctx->pracc_list[ctx->code_count].instr = instr;
+ ctx->pracc_list[ctx->code_count++].addr = addr;
+ if (addr)
+ ctx->store_count++;
}
-static int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
+void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize)
{
- uint32_t code[] = {
- /* start: */
- MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
- MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR), /* $15 = MIPS32_PRACC_BASE_ADDR */
- MIPS32_SW(8, PRACC_STACK_OFFSET, 15), /* sw $8,PRACC_STACK_OFFSET($15) */
-
- MIPS32_LUI(8, UPPER16((addr + 0x8000))), /* load $8 with modified upper address */
- MIPS32_LW(8, LOWER16(addr), 8), /* lw $8, LOWER16(addr)($8) */
- MIPS32_SW(8, PRACC_OUT_OFFSET, 15), /* sw $8,PRACC_OUT_OFFSET($15) */
-
- MIPS32_LW(8, PRACC_STACK_OFFSET, 15), /* lw $8,PRACC_STACK_OFFSET($15) */
- MIPS32_B(NEG16(8)), /* b start */
- MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
- };
+ if (LOWER16(data) == 0 && optimize)
+ pracc_add(ctx, 0, MIPS32_LUI(reg_num, UPPER16(data))); /* load only upper value */
+ else if (UPPER16(data) == 0 && optimize)
+ pracc_add(ctx, 0, MIPS32_ORI(reg_num, 0, LOWER16(data))); /* load only lower */
+ else {
+ pracc_add(ctx, 0, MIPS32_LUI(reg_num, UPPER16(data))); /* load upper and lower */
+ pracc_add(ctx, 0, MIPS32_ORI(reg_num, reg_num, LOWER16(data)));
+ }
+}
- return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 0, NULL, 1, buf, 1);
+inline void pracc_queue_free(struct pracc_queue_info *ctx)
+{
+ if (ctx->pracc_list != NULL)
+ free(ctx->pracc_list);
}
-int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
+int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *buf)
{
- if (count == 1 && size == 4)
- return mips32_pracc_read_u32(ejtag_info, addr, (uint32_t *)buf);
+ if (ctx->retval != ERROR_OK) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
- int retval = ERROR_FAIL;
+ if (ejtag_info->mode == 0)
+ return mips32_pracc_exec(ejtag_info, ctx, buf);
- uint32_t *code = NULL;
- uint32_t *data = NULL;
+ union scan_in {
+ uint8_t scan_96[12];
+ struct {
+ uint8_t ctrl[4];
+ uint8_t data[4];
+ uint8_t addr[4];
+ } scan_32;
- code = malloc((256 * 2 + 10) * sizeof(uint32_t));
- if (code == NULL) {
+ } *scan_in = malloc(sizeof(union scan_in) * (ctx->code_count + ctx->store_count));
+ if (scan_in == NULL) {
LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+
+ unsigned num_clocks =
+ ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000;
+
+ uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ALL);
+
+ int scan_count = 0;
+ for (int i = 0; i != ctx->code_count; i++) {
+ jtag_add_clocks(num_clocks);
+ mips_ejtag_add_scan_96(ejtag_info, ejtag_ctrl, ctx->pracc_list[i].instr,
+ scan_in[scan_count++].scan_96);
+
+ /* Check store address from previous instruction, if not the first */
+ if (i > 0 && ctx->pracc_list[i - 1].addr) {
+ jtag_add_clocks(num_clocks);
+ mips_ejtag_add_scan_96(ejtag_info, ejtag_ctrl, 0, scan_in[scan_count++].scan_96);
+ }
+ }
+
+ int retval = jtag_execute_queue(); /* execute queued scans */
+ if (retval != ERROR_OK)
goto exit;
+
+ uint32_t fetch_addr = MIPS32_PRACC_TEXT; /* start address */
+ scan_count = 0;
+ for (int i = 0; i != ctx->code_count; i++) { /* verify every pracc access */
+ /* check pracc bit */
+ ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32);
+ uint32_t addr = buf_get_u32(scan_in[scan_count].scan_32.addr, 0, 32);
+ if (!(ejtag_ctrl & EJTAG_CTRL_PRACC)) {
+ LOG_ERROR("Error: access not pending count: %d", scan_count);
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ if (ejtag_ctrl & EJTAG_CTRL_PRNW) {
+ LOG_ERROR("Not a fetch/read access, count: %d", scan_count);
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ if (addr != fetch_addr) {
+ LOG_ERROR("Fetch addr mismatch, read: %" PRIx32 " expected: %" PRIx32 " count: %d",
+ addr, fetch_addr, scan_count);
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ fetch_addr += 4;
+ scan_count++;
+
+ /* check if previous intrucction is a store instruction at dmesg */
+ if (i > 0 && ctx->pracc_list[i - 1].addr) {
+ uint32_t store_addr = ctx->pracc_list[i - 1].addr;
+ ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32);
+ addr = buf_get_u32(scan_in[scan_count].scan_32.addr, 0, 32);
+
+ if (!(ejtag_ctrl & EJTAG_CTRL_PRNW)) {
+ LOG_ERROR("Not a store/write access, count: %d", scan_count);
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ if (addr != store_addr) {
+ LOG_ERROR("Store address mismatch, read: %" PRIx32 " expected: %" PRIx32 " count: %d",
+ addr, store_addr, scan_count);
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ int buf_index = (addr - MIPS32_PRACC_PARAM_OUT) / 4;
+ buf[buf_index] = buf_get_u32(scan_in[scan_count].scan_32.data, 0, 32);
+ scan_count++;
+ }
}
+exit:
+ free(scan_in);
+ return retval;
+}
+
+int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
+{
+ struct pracc_queue_info ctx;
+ pracc_queue_init(&ctx);
+
+ pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
+ pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16((addr + 0x8000)))); /* load $8 with modified upper address */
+ pracc_add(&ctx, 0, MIPS32_LW(8, LOWER16(addr), 8)); /* lw $8, LOWER16(addr)($8) */
+ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
+ MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* sw $8,PRACC_OUT_OFFSET($15) */
+ pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, buf);
+ pracc_queue_free(&ctx);
+ return ctx.retval;
+}
+
+int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
+{
+ if (count == 1 && size == 4)
+ return mips32_pracc_read_u32(ejtag_info, addr, (uint32_t *)buf);
+
+ uint32_t *data = NULL;
+ struct pracc_queue_info ctx;
+ pracc_queue_init(&ctx);
if (size != 4) {
data = malloc(256 * sizeof(uint32_t));
uint16_t *buf16 = buf;
uint8_t *buf8 = buf;
- int i;
- uint32_t upper_base_addr, last_upper_base_addr;
- int this_round_count;
- int code_len;
-
while (count) {
- this_round_count = (count > 256) ? 256 : count;
- last_upper_base_addr = UPPER16((addr + 0x8000));
- uint32_t *code_p = code;
-
- *code_p++ = MIPS32_MTC0(15, 31, 0); /* save $15 in DeSave */
- *code_p++ = MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR); /* $15 = MIPS32_PRACC_BASE_ADDR */
- *code_p++ = MIPS32_SW(8, PRACC_STACK_OFFSET, 15); /* save $8 and $9 to pracc stack */
- *code_p++ = MIPS32_SW(9, PRACC_STACK_OFFSET, 15);
- *code_p++ = MIPS32_LUI(9, last_upper_base_addr); /* load the upper memory address in $9*/
- code_len = 5;
-
- for (i = 0; i != this_round_count; i++) { /* Main code loop */
- upper_base_addr = UPPER16((addr + 0x8000));
- if (last_upper_base_addr != upper_base_addr) {
- *code_p++ = MIPS32_LUI(9, upper_base_addr); /* if needed, change upper address in $9*/
- code_len++;
+ ctx.code_count = 0;
+ ctx.store_count = 0;
+ int this_round_count = (count > 256) ? 256 : count;
+ uint32_t last_upper_base_addr = UPPER16((addr + 0x8000));
+
+ pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
+ pracc_add(&ctx, 0, MIPS32_LUI(9, last_upper_base_addr)); /* load the upper memory address in $9 */
+
+ for (int i = 0; i != this_round_count; i++) { /* Main code loop */
+ uint32_t upper_base_addr = UPPER16((addr + 0x8000));
+ if (last_upper_base_addr != upper_base_addr) { /* if needed, change upper address in $9 */
+ pracc_add(&ctx, 0, MIPS32_LUI(9, upper_base_addr));
last_upper_base_addr = upper_base_addr;
}
if (size == 4)
- *code_p++ = MIPS32_LW(8, LOWER16(addr), 9); /* load from memory to $8 */
+ pracc_add(&ctx, 0, MIPS32_LW(8, LOWER16(addr), 9)); /* load from memory to $8 */
else if (size == 2)
- *code_p++ = MIPS32_LHU(8, LOWER16(addr), 9);
+ pracc_add(&ctx, 0, MIPS32_LHU(8, LOWER16(addr), 9));
else
- *code_p++ = MIPS32_LBU(8, LOWER16(addr), 9);
+ pracc_add(&ctx, 0, MIPS32_LBU(8, LOWER16(addr), 9));
- *code_p++ = MIPS32_SW(8, PRACC_OUT_OFFSET + i * 4, 15); /* store $8 at param out */
-
- code_len += 2;
+ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + i * 4,
+ MIPS32_SW(8, PRACC_OUT_OFFSET + i * 4, 15)); /* store $8 at param out */
addr += size;
}
+ pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */
+ pracc_add_li32(&ctx, 9, ejtag_info->reg9, 0); /* restore $9 */
- *code_p++ = MIPS32_LW(9, PRACC_STACK_OFFSET, 15); /* restore $8 and $9 from pracc stack */
- *code_p++ = MIPS32_LW(8, PRACC_STACK_OFFSET, 15);
-
- code_len += 4;
- *code_p++ = MIPS32_B(NEG16(code_len - 1)); /* jump to start */
- *code_p = MIPS32_MFC0(15, 31, 0); /* restore $15 from DeSave */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
if (size == 4) {
- retval = mips32_pracc_exec(ejtag_info, code_len, code, 0, NULL, this_round_count, buf32, 1);
- if (retval != ERROR_OK)
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, buf32);
+ if (ctx.retval != ERROR_OK)
goto exit;
buf32 += this_round_count;
} else {
- retval = mips32_pracc_exec(ejtag_info, code_len, code, 0, NULL, this_round_count, data, 1);
- if (retval != ERROR_OK)
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, data);
+ if (ctx.retval != ERROR_OK)
goto exit;
+
uint32_t *data_p = data;
- for (i = 0; i != this_round_count; i++) {
+ for (int i = 0; i != this_round_count; i++) {
if (size == 2)
*buf16++ = *data_p++;
else
}
count -= this_round_count;
}
-
exit:
- if (code)
- free(code);
- if (data)
+ pracc_queue_free(&ctx);
+ if (data != NULL)
free(data);
- return retval;
+ return ctx.retval;
}
int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel)
{
- /**
- * Do not make this code static, but regenerate it every time,
- * as 3th element has to be changed to add parameters
- */
- uint32_t code[] = {
- /* start: */
- MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
- MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR), /* $15 = MIPS32_PRACC_BASE_ADDR */
- MIPS32_SW(8, PRACC_STACK_OFFSET, 15), /* sw $8,PRACC_STACK_OFFSET($15) */
-
- /* 3 */ MIPS32_MFC0(8, 0, 0), /* move COP0 [cp0_reg select] to $8 */
- MIPS32_SW(8, PRACC_OUT_OFFSET, 15), /* sw $8,PRACC_OUT_OFFSET($15) */
-
- MIPS32_LW(8, PRACC_STACK_OFFSET, 15), /* lw $8,PRACC_STACK_OFFSET($15) */
- MIPS32_B(NEG16(7)), /* b start */
- MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
- };
-
- /**
- * Note that our input parametes cp0_reg and cp0_sel
- * are numbers (not gprs) which make part of mfc0 instruction opcode.
- *
- * These are not fix, but can be different for each mips32_cp0_read() function call,
- * and that is why we must insert them directly into opcode,
- * i.e. we can not pass it on EJTAG microprogram stack (via param_in),
- * and put them into the gprs later from MIPS32_PRACC_STACK
- * because mfc0 do not use gpr as a parameter for the cp0_reg and select part,
- * but plain (immediate) number.
- *
- * MIPS32_MTC0 is implemented via MIPS32_R_INST macro.
- * In order to insert our parameters, we must change rd and funct fields.
- */
- code[3] |= (cp0_reg << 11) | cp0_sel; /* change rd and funct of MIPS32_R_INST macro */
-
- return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 0, NULL, 1, val, 1);
+ struct pracc_queue_info ctx;
+ pracc_queue_init(&ctx);
+
+ pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
+ pracc_add(&ctx, 0, MIPS32_MFC0(8, cp0_reg, cp0_sel)); /* move cp0 reg / sel to $8 */
+ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
+ MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
+ pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
+ pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val);
+ pracc_queue_free(&ctx);
+ return ctx.retval;
}
int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
{
- uint32_t code[] = {
- /* start: */
- MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
- MIPS32_LUI(15, UPPER16(val)), /* Load val to $15 */
- MIPS32_ORI(15, 15, LOWER16(val)),
+ struct pracc_queue_info ctx;
+ pracc_queue_init(&ctx);
- /* 3 */ MIPS32_MTC0(15, 0, 0), /* move $15 to COP0 [cp0_reg select] */
+ pracc_add_li32(&ctx, 15, val, 0); /* Load val to $15 */
- MIPS32_B(NEG16(5)), /* b start */
- MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
- };
-
- /**
- * Note that MIPS32_MTC0 macro is implemented via MIPS32_R_INST macro.
- * In order to insert our parameters, we must change rd and funct fields.
- */
- code[3] |= (cp0_reg << 11) | cp0_sel; /* change rd and funct fields of MIPS32_R_INST macro */
+ pracc_add(&ctx, 0, MIPS32_MTC0(15, cp0_reg, cp0_sel)); /* write $15 to cp0 reg / sel */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
- return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 0, NULL, 0, NULL, 1);
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
+ pracc_queue_free(&ctx);
+ return ctx.retval;
}
/**
* to write back any containing D-cache line and invalidate any locations
* already in the I-cache.
*
- * You can do that with cache instructions, but those instructions are only available in kernel mode,
- * and a loader writing instructions for the use of its own process need not be privileged software.
+ * If the cache coherency attribute (CCA) is set to zero, it's a write through cache, there is no need
+ * to write back.
*
* In the latest MIPS32/64 CPUs, MIPS provides the synci instruction,
* which does the whole job for a cache-line-sized chunk of the memory you just loaded:
- * That is, it arranges a D-cache write-back and an I-cache invalidate.
+ * That is, it arranges a D-cache write-back (if CCA = 3) and an I-cache invalidate.
*
- * To employ synci at user level, you need to know the size of a cache line,
- * and that can be obtained with a rdhwr SYNCI_Step
- * from one of the standard “hardware registers”.
+ * The line size is obtained with the rdhwr SYNCI_Step in release 2 or from cp0 config 1 register in release 1.
*/
-static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info,
- uint32_t start_addr, uint32_t end_addr)
+static int mips32_pracc_synchronize_cache(struct mips_ejtag *ejtag_info,
+ uint32_t start_addr, uint32_t end_addr, int cached, int rel)
{
- static const uint32_t code[] = {
- /* start: */
- MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
- MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
- MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
- MIPS32_SW(8, 0, 15), /* sw $8,($15) */
- MIPS32_SW(9, 0, 15), /* sw $9,($15) */
- MIPS32_SW(10, 0, 15), /* sw $10,($15) */
- MIPS32_SW(11, 0, 15), /* sw $11,($15) */
-
- MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
- MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)),
- MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */
- MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */
-
- MIPS32_RDHWR(11, MIPS32_SYNCI_STEP), /* $11 = MIPS32_SYNCI_STEP */
- MIPS32_BEQ(11, 0, 6), /* beq $11, $0, end */
- MIPS32_NOP,
- /* synci_loop : */
- MIPS32_SYNCI(0, 9), /* synci 0($9) */
- MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */
- MIPS32_BNE(8, 0, NEG16(3)), /* bne $8, $0, synci_loop */
- MIPS32_ADDU(9, 9, 11), /* $9 += MIPS32_SYNCI_STEP */
- MIPS32_SYNC,
- /* end: */
- MIPS32_LW(11, 0, 15), /* lw $11,($15) */
- MIPS32_LW(10, 0, 15), /* lw $10,($15) */
- MIPS32_LW(9, 0, 15), /* lw $9,($15) */
- MIPS32_LW(8, 0, 15), /* lw $8,($15) */
- MIPS32_B(NEG16(24)), /* b start */
- MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
- };
+ struct pracc_queue_info ctx;
+ pracc_queue_init(&ctx);
- /* TODO remove array */
- uint32_t *param_in = malloc(2 * sizeof(uint32_t));
- int retval;
- param_in[0] = start_addr;
- param_in[1] = end_addr;
+ /** Find cache line size in bytes */
+ uint32_t clsiz;
+ if (rel) { /* Release 2 (rel = 1) */
+ pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
- retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 2, param_in, 0, NULL, 1);
+ pracc_add(&ctx, 0, MIPS32_RDHWR(8, MIPS32_SYNCI_STEP)); /* load synci_step value to $8 */
- free(param_in);
+ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
+ MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
- return retval;
-}
+ pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */
-/**
- * \b mips32_pracc_clean_invalidate_cache
- *
- * Writeback D$ and Invalidate I$
- * so that the instructions written can be visible to CPU
- */
-static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info,
- uint32_t start_addr, uint32_t end_addr)
-{
- static const uint32_t code[] = {
- /* start: */
- MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
- MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
- MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
- MIPS32_SW(8, 0, 15), /* sw $8,($15) */
- MIPS32_SW(9, 0, 15), /* sw $9,($15) */
- MIPS32_SW(10, 0, 15), /* sw $10,($15) */
- MIPS32_SW(11, 0, 15), /* sw $11,($15) */
-
- MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
- MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)),
- MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */
- MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */
- MIPS32_LW(11, 8, 8), /* Load write clsiz to $11 */
-
- /* cache_loop: */
- MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 : $8 <- $10 < $9 ? */
- MIPS32_BGTZ(8, 6), /* bgtz $8, end */
- MIPS32_NOP,
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
- MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK, 0, 9), /* cache Hit_Writeback_D, 0($9) */
- MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE, 0, 9), /* cache Hit_Invalidate_I, 0($9) */
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, &clsiz);
+ if (ctx.retval != ERROR_OK)
+ goto exit;
- MIPS32_ADDU(9, 9, 11), /* $9 += $11 */
+ } else { /* Release 1 (rel = 0) */
+ uint32_t conf;
+ ctx.retval = mips32_cp0_read(ejtag_info, &conf, 16, 1);
+ if (ctx.retval != ERROR_OK)
+ goto exit;
- MIPS32_B(NEG16(7)), /* b cache_loop */
- MIPS32_NOP,
- /* end: */
- MIPS32_LW(11, 0, 15), /* lw $11,($15) */
- MIPS32_LW(10, 0, 15), /* lw $10,($15) */
- MIPS32_LW(9, 0, 15), /* lw $9,($15) */
- MIPS32_LW(8, 0, 15), /* lw $8,($15) */
- MIPS32_B(NEG16(25)), /* b start */
- MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
- };
+ uint32_t dl = (conf & MIPS32_CONFIG1_DL_MASK) >> MIPS32_CONFIG1_DL_SHIFT;
- /**
- * Find cache line size in bytes
- */
- uint32_t conf;
- uint32_t dl, clsiz;
+ /* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... max dl=6 => 128 bytes cache line size */
+ clsiz = 0x2 << dl;
+ if (dl == 0)
+ clsiz = 0;
+ }
+
+ if (clsiz == 0)
+ goto exit; /* Nothing to do */
+
+ /* make sure clsiz is power of 2 */
+ if (clsiz & (clsiz - 1)) {
+ LOG_DEBUG("clsiz must be power of 2");
+ ctx.retval = ERROR_FAIL;
+ goto exit;
+ }
- mips32_cp0_read(ejtag_info, &conf, 16, 1);
- dl = (conf & MIPS32_CONFIG1_DL_MASK) >> MIPS32_CONFIG1_DL_SHIFT;
+ /* make sure start_addr and end_addr have the same offset inside de cache line */
+ start_addr |= clsiz - 1;
+ end_addr |= clsiz - 1;
- /* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... */
- clsiz = 0x2 << dl;
+ ctx.code_count = 0;
+ int count = 0;
+ uint32_t last_upper_base_addr = UPPER16((start_addr + 0x8000));
- /* TODO remove array */
- uint32_t *param_in = malloc(3 * sizeof(uint32_t));
- int retval;
- param_in[0] = start_addr;
- param_in[1] = end_addr;
- param_in[2] = clsiz;
+ pracc_add(&ctx, 0, MIPS32_LUI(15, last_upper_base_addr)); /* load upper memory base address to $15 */
- retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 3, param_in, 0, NULL, 1);
+ while (start_addr <= end_addr) { /* main loop */
+ uint32_t upper_base_addr = UPPER16((start_addr + 0x8000));
+ if (last_upper_base_addr != upper_base_addr) { /* if needed, change upper address in $15 */
+ pracc_add(&ctx, 0, MIPS32_LUI(15, upper_base_addr));
+ last_upper_base_addr = upper_base_addr;
+ }
+ if (rel)
+ pracc_add(&ctx, 0, MIPS32_SYNCI(LOWER16(start_addr), 15)); /* synci instruction, offset($15) */
- free(param_in);
+ else {
+ if (cached == 3)
+ pracc_add(&ctx, 0, MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK,
+ LOWER16(start_addr), 15)); /* cache Hit_Writeback_D, offset($15) */
- return retval;
-}
+ pracc_add(&ctx, 0, MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE,
+ LOWER16(start_addr), 15)); /* cache Hit_Invalidate_I, offset($15) */
+ }
+ start_addr += clsiz;
+ count++;
+ if (count == 256 && start_addr <= end_addr) { /* more ?, then execute code list */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_NOP); /* nop in delay slot */
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
+ if (ctx.retval != ERROR_OK)
+ goto exit;
-static int mips32_pracc_write_mem_generic(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
-{
- uint32_t *code;
- code = malloc((128 * 3 + 9) * sizeof(uint32_t)); /* alloc memory for the worst case */
- if (code == NULL) {
- LOG_ERROR("Out of memory");
- return ERROR_FAIL;
+ ctx.code_count = 0;
+ count = 0;
+ }
}
+ pracc_add(&ctx, 0, MIPS32_SYNC);
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave*/
- uint32_t *buf32 = buf;
- uint16_t *buf16 = buf;
- uint8_t *buf8 = buf;
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
+exit:
+ pracc_queue_free(&ctx);
+ return ctx.retval;
+}
- int i;
- int retval = ERROR_FAIL;
- uint32_t *code_p;
- uint32_t upper_base_addr, last_upper_base_addr;
- int this_round_count;
- int code_len;
+static int mips32_pracc_write_mem_generic(struct mips_ejtag *ejtag_info,
+ uint32_t addr, int size, int count, const void *buf)
+{
+ struct pracc_queue_info ctx;
+ pracc_queue_init(&ctx);
+
+ const uint32_t *buf32 = buf;
+ const uint16_t *buf16 = buf;
+ const uint8_t *buf8 = buf;
while (count) {
- this_round_count = (count > 128) ? 128 : count;
- last_upper_base_addr = UPPER16((addr + 0x8000));
- code_p = code;
-
- *code_p++ = MIPS32_MTC0(15, 31, 0); /* save $15 in DeSave */
- *code_p++ = MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR); /* $15 = MIPS32_PRACC_BASE_ADDR */
- *code_p++ = MIPS32_SW(8, PRACC_STACK_OFFSET, 15); /* save $8 to pracc stack */
- *code_p++ = MIPS32_LUI(15, last_upper_base_addr); /* reuse $15 as memory base address */
- code_len = 4;
-
- for (i = 0; i != this_round_count; i++) {
- upper_base_addr = UPPER16((addr + 0x8000));
+ ctx.code_count = 0;
+ ctx.store_count = 0;
+ int this_round_count = (count > 128) ? 128 : count;
+ uint32_t last_upper_base_addr = UPPER16((addr + 0x8000));
+
+ pracc_add(&ctx, 0, MIPS32_LUI(15, last_upper_base_addr)); /* load $15 with memory base address */
+
+ for (int i = 0; i != this_round_count; i++) {
+ uint32_t upper_base_addr = UPPER16((addr + 0x8000));
if (last_upper_base_addr != upper_base_addr) {
- *code_p++ = MIPS32_LUI(15, upper_base_addr); /* if needed, change upper address in $15*/
- code_len++;
+ pracc_add(&ctx, 0, MIPS32_LUI(15, upper_base_addr)); /* if needed, change upper address in $15*/
last_upper_base_addr = upper_base_addr;
}
- if (size == 4) { /* for word write check if one half word is 0 and load it accordingly */
- if (LOWER16(*buf32) == 0) {
- *code_p++ = MIPS32_LUI(8, UPPER16(*buf32)); /* load only upper value */
- code_len++;
- } else if (UPPER16(*buf32) == 0) {
- *code_p++ = MIPS32_ORI(8, 0, LOWER16(*buf32)); /* load only lower value */
- code_len++;
- } else {
- *code_p++ = MIPS32_LUI(8, UPPER16(*buf32)); /* load upper and lower */
- *code_p++ = MIPS32_ORI(8, 8, LOWER16(*buf32));
- code_len += 2;
- }
- *code_p++ = MIPS32_SW(8, LOWER16(addr), 15); /* store word to memory */
- code_len++;
+ if (size == 4) {
+ pracc_add_li32(&ctx, 8, *buf32, 1); /* load with li32, optimize */
+ pracc_add(&ctx, 0, MIPS32_SW(8, LOWER16(addr), 15)); /* store word to memory */
buf32++;
} else if (size == 2) {
- *code_p++ = MIPS32_ORI(8, 0, *buf16); /* load lower value */
- *code_p++ = MIPS32_SH(8, LOWER16(addr), 15); /* store half word to memory */
- code_len += 2;
+ pracc_add(&ctx, 0, MIPS32_ORI(8, 0, *buf16)); /* load lower value */
+ pracc_add(&ctx, 0, MIPS32_SH(8, LOWER16(addr), 15)); /* store half word to memory */
buf16++;
} else {
- *code_p++ = MIPS32_ORI(8, 0, *buf8); /* load lower value */
- *code_p++ = MIPS32_SB(8, LOWER16(addr), 15); /* store byte to memory */
- code_len += 2;
+ pracc_add(&ctx, 0, MIPS32_ORI(8, 0, *buf8)); /* load lower value */
+ pracc_add(&ctx, 0, MIPS32_SB(8, LOWER16(addr), 15)); /* store byte to memory */
buf8++;
}
-
addr += size;
}
- *code_p++ = MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR); /* $15 = MIPS32_PRACC_BASE_ADDR */
- *code_p++ = MIPS32_LW(8, PRACC_STACK_OFFSET, 15); /* restore $8 from pracc stack */
+ pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */
- code_len += 4;
- *code_p++ = MIPS32_B(NEG16(code_len - 1)); /* jump to start */
- *code_p = MIPS32_MFC0(15, 31, 0); /* restore $15 from DeSave */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
- retval = mips32_pracc_exec(ejtag_info, code_len, code, 0, NULL, 0, NULL, 1);
- if (retval != ERROR_OK)
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
+ if (ctx.retval != ERROR_OK)
goto exit;
-
count -= this_round_count;
}
-
exit:
- free(code);
- return retval;
+ pracc_queue_free(&ctx);
+ return ctx.retval;
}
-int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
+int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf)
{
int retval = mips32_pracc_write_mem_generic(ejtag_info, addr, size, count, buf);
if (retval != ERROR_OK)
return retval;
/**
- * If we are in the cachable regoion and cache is activated,
- * we must clean D$ + invalidate I$ after we did the write,
- * so that changes do not continue to live only in D$, but to be
+ * If we are in the cacheable region and cache is activated,
+ * we must clean D$ (if Cache Coherency Attribute is set to 3) + invalidate I$ after we did the write,
+ * so that changes do not continue to live only in D$ (if CCA = 3), but to be
* replicated in I$ also (maybe we wrote the istructions)
*/
uint32_t conf = 0;
}
/**
- * Check cachablitiy bits coherency algorithm -
+ * Check cachablitiy bits coherency algorithm
* is the region cacheable or uncached.
* If cacheable we have to synchronize the cache
*/
- if (cached == 0x3) {
- uint32_t start_addr, end_addr;
- uint32_t rel;
-
- start_addr = addr;
- end_addr = addr + count * size;
-
- /** select cache synchronisation mechanism based on Architecture Release */
- rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
- switch (rel) {
- case MIPS32_ARCH_REL1:
- /* MIPS32/64 Release 1 - we must use cache instruction */
- mips32_pracc_clean_invalidate_cache(ejtag_info, start_addr, end_addr);
- break;
- case MIPS32_ARCH_REL2:
- /* MIPS32/64 Release 2 - we can use synci instruction */
- mips32_pracc_sync_cache(ejtag_info, start_addr, end_addr);
- break;
- default:
- /* what ? */
- break;
+ if (cached == 3 || cached == 0) { /* Write back cache or write through cache */
+ uint32_t start_addr = addr;
+ uint32_t end_addr = addr + count * size;
+ uint32_t rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
+ if (rel > 1) {
+ LOG_DEBUG("Unknown release in cache code");
+ return ERROR_FAIL;
}
+ retval = mips32_pracc_synchronize_cache(ejtag_info, start_addr, end_addr, cached, rel);
}
return retval;
MIPS32_MTC0(1, 24, 0), /* move $1 to depc (pc) */
};
- uint32_t *code;
- code = malloc((37 * 2 + 6 + 1) * sizeof(uint32_t)); /* alloc memory for the worst case */
- if (code == NULL) {
- LOG_ERROR("Out of memory");
- return ERROR_FAIL;
- }
+ struct pracc_queue_info ctx;
+ pracc_queue_init(&ctx);
- uint32_t *code_p = code;
- int code_len = 0;
- /* load registers 2 to 31 with lui an ori instructions, check if same instructions can be saved */
- for (int i = 2; i < 32; i++) {
- if (LOWER16((regs[i])) == 0) {
- *code_p++ = MIPS32_LUI(i, UPPER16((regs[i]))); /* if lower half word is 0, lui instruction only */
- code_len++;
- } else if (UPPER16((regs[i])) == 0) {
- *code_p++ = MIPS32_ORI(i, 0, LOWER16((regs[i]))); /* if upper half word is 0, ori with $0 only*/
- code_len++;
- } else {
- *code_p++ = MIPS32_LUI(i, UPPER16((regs[i]))); /* default, load with lui and ori instructions */
- *code_p++ = MIPS32_ORI(i, i, LOWER16((regs[i])));
- code_len += 2;
- }
- }
+ /* load registers 2 to 31 with li32, optimize */
+ for (int i = 2; i < 32; i++)
+ pracc_add_li32(&ctx, i, regs[i], 1);
for (int i = 0; i != 6; i++) {
- *code_p++ = MIPS32_LUI(1, UPPER16((regs[i + 32]))); /* load CPO value in $1, with lui and ori */
- *code_p++ = MIPS32_ORI(1, 1, LOWER16((regs[i + 32])));
- *code_p++ = cp0_write_code[i]; /* write value from $1 to CPO register */
- code_len += 3;
+ pracc_add_li32(&ctx, 1, regs[i + 32], 0); /* load CPO value in $1 */
+ pracc_add(&ctx, 0, cp0_write_code[i]); /* write value from $1 to CPO register */
}
+ pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* load $15 in DeSave */
+ pracc_add(&ctx, 0, MIPS32_LUI(1, UPPER16((regs[1])))); /* load upper half word in $1 */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_ORI(1, 1, LOWER16((regs[1])))); /* load lower half word in $1 */
- *code_p++ = MIPS32_LUI(1, UPPER16((regs[1]))); /* load upper half word in $1 */
- code_len += 3;
- *code_p++ = MIPS32_B(NEG16(code_len - 1)), /* b start */
- *code_p = MIPS32_ORI(1, 1, LOWER16((regs[1]))); /* load lower half word in $1 */
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
- int retval = mips32_pracc_exec(ejtag_info, code_len, code, 0, NULL, 0, NULL, 1);
- free(code);
- return retval;
+ ejtag_info->reg8 = regs[8];
+ ejtag_info->reg9 = regs[9];
+ pracc_queue_free(&ctx);
+ return ctx.retval;
}
int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
{
static int cp0_read_code[] = {
- MIPS32_MFC0(2, 12, 0), /* move status to $2 */
- MIPS32_MFLO(2), /* move lo to $2 */
- MIPS32_MFHI(2), /* move hi to $2 */
- MIPS32_MFC0(2, 8, 0), /* move badvaddr to $2 */
- MIPS32_MFC0(2, 13, 0), /* move cause to $2 */
- MIPS32_MFC0(2, 24, 0), /* move depc (pc) to $2 */
+ MIPS32_MFC0(8, 12, 0), /* move status to $8 */
+ MIPS32_MFLO(8), /* move lo to $8 */
+ MIPS32_MFHI(8), /* move hi to $8 */
+ MIPS32_MFC0(8, 8, 0), /* move badvaddr to $8 */
+ MIPS32_MFC0(8, 13, 0), /* move cause to $8 */
+ MIPS32_MFC0(8, 24, 0), /* move depc (pc) to $8 */
};
- uint32_t *code;
- code = malloc(49 * sizeof(uint32_t));
- if (code == NULL) {
- LOG_ERROR("Out of memory");
- return ERROR_FAIL;
- }
-
- uint32_t *code_p = code;
+ struct pracc_queue_info ctx;
+ pracc_queue_init(&ctx);
- *code_p++ = MIPS32_MTC0(1, 31, 0), /* move $1 to COP0 DeSave */
- *code_p++ = MIPS32_LUI(1, PRACC_UPPER_BASE_ADDR); /* $1 = MIP32_PRACC_BASE_ADDR */
+ pracc_add(&ctx, 0, MIPS32_MTC0(1, 31, 0)); /* move $1 to COP0 DeSave */
+ pracc_add(&ctx, 0, MIPS32_LUI(1, PRACC_UPPER_BASE_ADDR)); /* $1 = MIP32_PRACC_BASE_ADDR */
- for (int i = 2; i != 32; i++)
- *code_p++ = MIPS32_SW(i, PRACC_OUT_OFFSET + (i * 4), 1); /* store GPR's 2 to 31 */
+ for (int i = 2; i != 32; i++) /* store GPR's 2 to 31 */
+ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i * 4),
+ MIPS32_SW(i, PRACC_OUT_OFFSET + (i * 4), 1));
for (int i = 0; i != 6; i++) {
- *code_p++ = cp0_read_code[i]; /* load COP0 needed registers to $2 */
- *code_p++ = MIPS32_SW(2, PRACC_OUT_OFFSET + (i + 32) * 4, 1); /* store COP0 registers from $2 to param out */
+ pracc_add(&ctx, 0, cp0_read_code[i]); /* load COP0 needed registers to $8 */
+ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i + 32) * 4, /* store $8 at PARAM OUT */
+ MIPS32_SW(8, PRACC_OUT_OFFSET + (i + 32) * 4, 1));
}
+ pracc_add(&ctx, 0, MIPS32_MFC0(8, 31, 0)); /* move DeSave to $8, reg1 value */
+ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + 4, /* store reg1 value from $8 to param out */
+ MIPS32_SW(8, PRACC_OUT_OFFSET + 4, 1));
- *code_p++ = MIPS32_MFC0(2, 31, 0), /* move DeSave to $2, reg1 value */
- *code_p++ = MIPS32_SW(2, PRACC_OUT_OFFSET + 4, 1); /* store reg1 value from $2 to param out */
+ pracc_add(&ctx, 0, MIPS32_MFC0(1, 31, 0)); /* move COP0 DeSave to $1, restore reg1 */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* load $15 in DeSave */
- *code_p++ = MIPS32_LW(2, PRACC_OUT_OFFSET + 8, 1); /* restore $2 from param out (singularity) */
- *code_p++ = MIPS32_B(NEG16(48)); /* b start */
- *code_p = MIPS32_MFC0(1, 31, 0); /* move COP0 DeSave to $1 */
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, regs);
- int retval = mips32_pracc_exec(ejtag_info, 49, code, 0, NULL, MIPS32NUMCOREREGS, regs, 1);
-
- free(code);
- return retval;
+ ejtag_info->reg8 = regs[8]; /* reg8 is saved but not restored, next called function should restore it */
+ ejtag_info->reg9 = regs[9];
+ pracc_queue_free(&ctx);
+ return ctx.retval;
}
/* fastdata upload/download requires an initialized working area
int write_t, uint32_t addr, int count, uint32_t *buf)
{
uint32_t handler_code[] = {
- /* caution when editing, table is modified below */
/* r15 points to the start of this code */
MIPS32_SW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15),
MIPS32_SW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15),
/* start of fastdata area in t0 */
MIPS32_LUI(8, UPPER16(MIPS32_PRACC_FASTDATA_AREA)),
MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_FASTDATA_AREA)),
- MIPS32_LW(9, 0, 8), /* start addr in t1 */
- MIPS32_LW(10, 0, 8), /* end addr to t2 */
- /* loop: */
- /* 8 */ MIPS32_LW(11, 0, 0), /* lw t3,[t8 | r9] */
- /* 9 */ MIPS32_SW(11, 0, 0), /* sw t3,[r9 | r8] */
- MIPS32_BNE(10, 9, NEG16(3)), /* bne $t2,t1,loop */
- MIPS32_ADDI(9, 9, 4), /* addi t1,t1,4 */
+ MIPS32_LW(9, 0, 8), /* start addr in t1 */
+ MIPS32_LW(10, 0, 8), /* end addr to t2 */
+ /* loop: */
+ write_t ? MIPS32_LW(11, 0, 8) : MIPS32_LW(11, 0, 9), /* from xfer area : from memory */
+ write_t ? MIPS32_SW(11, 0, 9) : MIPS32_SW(11, 0, 8), /* to memory : to xfer area */
+
+ MIPS32_BNE(10, 9, NEG16(3)), /* bne $t2,t1,loop */
+ MIPS32_ADDI(9, 9, 4), /* addi t1,t1,4 */
MIPS32_LW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15),
MIPS32_LW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15),
MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
};
- uint32_t jmp_code[] = {
- MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
- /* 1 */ MIPS32_LUI(15, 0), /* addr of working area added below */
- /* 2 */ MIPS32_ORI(15, 15, 0), /* addr of working area added below */
- MIPS32_JR(15), /* jump to ram program */
- MIPS32_NOP,
- };
-
- int retval, i;
- uint32_t val, ejtag_ctrl, address;
-
if (source->size < MIPS32_FASTDATA_HANDLER_SIZE)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- if (write_t) {
- handler_code[8] = MIPS32_LW(11, 0, 8); /* load data from probe at fastdata area */
- handler_code[9] = MIPS32_SW(11, 0, 9); /* store data to RAM @ r9 */
- } else {
- handler_code[8] = MIPS32_LW(11, 0, 9); /* load data from RAM @ r9 */
- handler_code[9] = MIPS32_SW(11, 0, 8); /* store data to probe at fastdata area */
- }
-
- /* write program into RAM */
+ /* write program into RAM */
if (write_t != ejtag_info->fast_access_save) {
- mips32_pracc_write_mem_generic(ejtag_info, source->address, 4, ARRAY_SIZE(handler_code), handler_code);
+ mips32_pracc_write_mem(ejtag_info, source->address, 4, ARRAY_SIZE(handler_code), handler_code);
/* save previous operation to speed to any consecutive read/writes */
ejtag_info->fast_access_save = write_t;
}
- LOG_DEBUG("%s using 0x%.8" PRIx32 " for write handler", __func__, source->address);
+ LOG_DEBUG("%s using 0x%.8" TARGET_PRIxADDR " for write handler", __func__, source->address);
- jmp_code[1] |= UPPER16(source->address);
- jmp_code[2] |= LOWER16(source->address);
+ uint32_t jmp_code[] = {
+ MIPS32_LUI(15, UPPER16(source->address)), /* load addr of jump in $15 */
+ MIPS32_ORI(15, 15, LOWER16(source->address)),
+ MIPS32_JR(15), /* jump to ram program */
+ MIPS32_NOP,
+ };
- for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++) {
- retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
+ /* execute jump code, with no address check */
+ for (unsigned i = 0; i < ARRAY_SIZE(jmp_code); i++) {
+ int retval = wait_for_pracc_rw(ejtag_info);
if (retval != ERROR_OK)
return retval;
mips_ejtag_drscan_32_out(ejtag_info, jmp_code[i]);
/* Clear the access pending bit (let the processor eat!) */
- ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
- mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
+ mips32_pracc_finish(ejtag_info);
}
- /* wait PrAcc pending bit for FASTDATA write */
- retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
+ /* wait PrAcc pending bit for FASTDATA write, read address */
+ int retval = mips32_pracc_read_ctrl_addr(ejtag_info);
if (retval != ERROR_OK)
return retval;
/* next fetch to dmseg should be in FASTDATA_AREA, check */
- address = 0;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
- retval = mips_ejtag_drscan_32(ejtag_info, &address);
- if (retval != ERROR_OK)
- return retval;
-
- if (address != MIPS32_PRACC_FASTDATA_AREA)
+ if (ejtag_info->pa_addr != MIPS32_PRACC_FASTDATA_AREA)
return ERROR_FAIL;
/* Send the load start address */
- val = addr;
+ uint32_t val = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
- retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
+ retval = wait_for_pracc_rw(ejtag_info);
if (retval != ERROR_OK)
return retval;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
- for (i = 0; i < count; i++) {
- retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++);
- if (retval != ERROR_OK)
- return retval;
+ unsigned num_clocks = 0; /* like in legacy code */
+ if (ejtag_info->mode != 0)
+ num_clocks = ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000;
+
+ for (int i = 0; i < count; i++) {
+ jtag_add_clocks(num_clocks);
+ mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++);
}
retval = jtag_execute_queue();
return retval;
}
- retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
- if (retval != ERROR_OK)
- return retval;
-
- address = 0;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
- retval = mips_ejtag_drscan_32(ejtag_info, &address);
+ retval = mips32_pracc_read_ctrl_addr(ejtag_info);
if (retval != ERROR_OK)
return retval;
- if (address != MIPS32_PRACC_TEXT)
+ if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT)
LOG_ERROR("mini program did not return to start");
return retval;
Code Review / openocd.git / blobdiff