#include "mips32.h"
#include "mips32_pracc.h"
-static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl)
+static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info)
{
- uint32_t ejtag_ctrl;
int64_t then = timeval_ms();
/* wait for the PrAcc to become "1" */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
while (1) {
- ejtag_ctrl = ejtag_info->ejtag_ctrl;
- int retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ ejtag_info->pa_ctrl = ejtag_info->ejtag_ctrl;
+ int retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_info->pa_ctrl);
if (retval != ERROR_OK)
return retval;
- if (ejtag_ctrl & EJTAG_CTRL_PRACC)
+ if (ejtag_info->pa_ctrl & EJTAG_CTRL_PRACC)
break;
int64_t timeout = timeval_ms() - then;
}
}
- *ctrl = ejtag_ctrl;
return ERROR_OK;
}
/* Shift in control and address for a new processor access, save them in ejtag_info */
static int mips32_pracc_read_ctrl_addr(struct mips_ejtag *ejtag_info)
{
- int retval = wait_for_pracc_rw(ejtag_info, &ejtag_info->pa_ctrl);
+ int retval = wait_for_pracc_rw(ejtag_info);
if (retval != ERROR_OK)
return retval;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
- ejtag_info->pa_addr = 0;
- retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_info->pa_addr);
- return retval;
+ ejtag_info->pa_addr = 0;
+ return mips_ejtag_drscan_32(ejtag_info, &ejtag_info->pa_addr);
}
/* Finish processor access */
-static int mips32_pracc_finish(struct mips_ejtag *ejtag_info)
+static void mips32_pracc_finish(struct mips_ejtag *ejtag_info)
{
uint32_t ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32_out(ejtag_info, ctrl);
-
- return jtag_execute_queue();
}
int mips32_pracc_clean_text_jump(struct mips_ejtag *ejtag_info)
{
uint32_t jt_code = MIPS32_J((0x0FFFFFFF & MIPS32_PRACC_TEXT) >> 2);
- int retval;
/* do 3 0/nops to clean pipeline before a jump to pracc text, NOP in delay slot */
for (int i = 0; i != 5; i++) {
/* Wait for pracc */
- retval = wait_for_pracc_rw(ejtag_info, &ejtag_info->pa_ctrl);
+ int retval = wait_for_pracc_rw(ejtag_info);
if (retval != ERROR_OK)
return retval;
mips_ejtag_drscan_32_out(ejtag_info, data);
/* finish pa */
- retval = mips32_pracc_finish(ejtag_info);
- if (retval != ERROR_OK)
- return retval;
+ mips32_pracc_finish(ejtag_info);
}
if (ejtag_info->mode != 0) /* async mode support only for MIPS ... */
return ERROR_OK;
for (int i = 0; i != 2; i++) {
- retval = mips32_pracc_read_ctrl_addr(ejtag_info);
+ int retval = mips32_pracc_read_ctrl_addr(ejtag_info);
if (retval != ERROR_OK)
return retval;
if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT) { /* LEXRA/BMIPS ?, shift out another NOP, max 2 */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32_out(ejtag_info, MIPS32_NOP);
- retval = mips32_pracc_finish(ejtag_info);
- if (retval != ERROR_OK)
- return retval;
+ mips32_pracc_finish(ejtag_info);
} else
break;
}
restart = 1;
continue;
}
-
return ERROR_JTAG_DEVICE_ERROR;
}
/* check for store instruction at dmseg */
- uint32_t store_addr = ctx->pracc_list[ctx->max_code + code_count];
+ uint32_t store_addr = ctx->pracc_list[code_count].addr;
if (store_addr != 0) {
if (store_addr > max_store_addr)
max_store_addr = store_addr;
store_pending++;
}
- instr = ctx->pracc_list[code_count++];
+ instr = ctx->pracc_list[code_count++].instr;
if (code_count == ctx->code_count) /* last instruction, start final check */
final_check = 1;
mips_ejtag_drscan_32_out(ejtag_info, instr);
}
/* finish processor access, let the processor eat! */
- retval = mips32_pracc_finish(ejtag_info);
- if (retval != ERROR_OK)
- return retval;
+ mips32_pracc_finish(ejtag_info);
if (instr == MIPS32_DRET) /* after leaving debug mode nothing to do */
- return ERROR_OK;
+ return jtag_execute_queue();
if (store_pending == 0 && pass) { /* store access done, but after passing pracc text */
LOG_DEBUG("warning: store access pass pracc text");
ctx->retval = ERROR_OK;
ctx->code_count = 0;
ctx->store_count = 0;
-
- ctx->pracc_list = malloc(2 * ctx->max_code * sizeof(uint32_t));
- if (ctx->pracc_list == NULL) {
- LOG_ERROR("Out of memory");
- ctx->retval = ERROR_FAIL;
- }
+ ctx->max_code = 0;
+ ctx->pracc_list = NULL;
}
-inline void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)
+void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)
{
- ctx->pracc_list[ctx->max_code + ctx->code_count] = addr;
- ctx->pracc_list[ctx->code_count++] = instr;
+ if (ctx->retval != ERROR_OK) /* On previous out of memory, return */
+ return;
+ if (ctx->code_count == ctx->max_code) {
+ void *p = realloc(ctx->pracc_list, sizeof(pa_list) * (ctx->max_code + PRACC_BLOCK));
+ if (p) {
+ ctx->max_code += PRACC_BLOCK;
+ ctx->pracc_list = p;
+ } else {
+ ctx->retval = ERROR_FAIL; /* Out of memory */
+ return;
+ }
+ }
+ ctx->pracc_list[ctx->code_count].instr = instr;
+ ctx->pracc_list[ctx->code_count++].addr = addr;
if (addr)
ctx->store_count++;
}
+void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize)
+{
+ if (LOWER16(data) == 0 && optimize)
+ pracc_add(ctx, 0, MIPS32_LUI(reg_num, UPPER16(data))); /* load only upper value */
+ else if (UPPER16(data) == 0 && optimize)
+ pracc_add(ctx, 0, MIPS32_ORI(reg_num, 0, LOWER16(data))); /* load only lower */
+ else {
+ pracc_add(ctx, 0, MIPS32_LUI(reg_num, UPPER16(data))); /* load upper and lower */
+ pracc_add(ctx, 0, MIPS32_ORI(reg_num, reg_num, LOWER16(data)));
+ }
+}
+
inline void pracc_queue_free(struct pracc_queue_info *ctx)
{
- if (ctx->code_count > ctx->max_code) /* Only for internal check, will be erased */
- LOG_ERROR("Internal error, code count: %d > max code: %d", ctx->code_count, ctx->max_code);
if (ctx->pracc_list != NULL)
free(ctx->pracc_list);
}
int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *buf)
{
+ if (ctx->retval != ERROR_OK) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+
if (ejtag_info->mode == 0)
return mips32_pracc_exec(ejtag_info, ctx, buf);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ALL);
int scan_count = 0;
- for (int i = 0; i != 2 * ctx->code_count; i++) {
- uint32_t data = 0;
- if (i & 1u) { /* Check store address from previous instruction, if not the first */
- if (i < 2 || 0 == ctx->pracc_list[ctx->max_code + (i / 2) - 1])
- continue;
- } else
- data = ctx->pracc_list[i / 2];
-
+ for (int i = 0; i != ctx->code_count; i++) {
jtag_add_clocks(num_clocks);
- mips_ejtag_add_scan_96(ejtag_info, ejtag_ctrl, data, scan_in[scan_count++].scan_96);
+ mips_ejtag_add_scan_96(ejtag_info, ejtag_ctrl, ctx->pracc_list[i].instr,
+ scan_in[scan_count++].scan_96);
+
+ /* Check store address from previous instruction, if not the first */
+ if (i > 0 && ctx->pracc_list[i - 1].addr) {
+ jtag_add_clocks(num_clocks);
+ mips_ejtag_add_scan_96(ejtag_info, ejtag_ctrl, 0, scan_in[scan_count++].scan_96);
+ }
}
int retval = jtag_execute_queue(); /* execute queued scans */
uint32_t fetch_addr = MIPS32_PRACC_TEXT; /* start address */
scan_count = 0;
- for (int i = 0; i != 2 * ctx->code_count; i++) { /* verify every pracc access */
- uint32_t store_addr = 0;
- if (i & 1u) { /* Read store addres from previous instruction, if not the first */
- store_addr = ctx->pracc_list[ctx->max_code + (i / 2) - 1];
- if (i < 2 || 0 == store_addr)
- continue;
- }
-
+ for (int i = 0; i != ctx->code_count; i++) { /* verify every pracc access */
+ /* check pracc bit */
ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32);
+ uint32_t addr = buf_get_u32(scan_in[scan_count].scan_32.addr, 0, 32);
if (!(ejtag_ctrl & EJTAG_CTRL_PRACC)) {
LOG_ERROR("Error: access not pending count: %d", scan_count);
retval = ERROR_FAIL;
goto exit;
}
+ if (ejtag_ctrl & EJTAG_CTRL_PRNW) {
+ LOG_ERROR("Not a fetch/read access, count: %d", scan_count);
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ if (addr != fetch_addr) {
+ LOG_ERROR("Fetch addr mismatch, read: %" PRIx32 " expected: %" PRIx32 " count: %d",
+ addr, fetch_addr, scan_count);
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ fetch_addr += 4;
+ scan_count++;
- uint32_t addr = buf_get_u32(scan_in[scan_count].scan_32.addr, 0, 32);
+ /* check if previous intrucction is a store instruction at dmesg */
+ if (i > 0 && ctx->pracc_list[i - 1].addr) {
+ uint32_t store_addr = ctx->pracc_list[i - 1].addr;
+ ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32);
+ addr = buf_get_u32(scan_in[scan_count].scan_32.addr, 0, 32);
- if (store_addr != 0) {
if (!(ejtag_ctrl & EJTAG_CTRL_PRNW)) {
LOG_ERROR("Not a store/write access, count: %d", scan_count);
retval = ERROR_FAIL;
}
if (addr != store_addr) {
LOG_ERROR("Store address mismatch, read: %" PRIx32 " expected: %" PRIx32 " count: %d",
- addr, store_addr, scan_count);
+ addr, store_addr, scan_count);
retval = ERROR_FAIL;
goto exit;
}
int buf_index = (addr - MIPS32_PRACC_PARAM_OUT) / 4;
buf[buf_index] = buf_get_u32(scan_in[scan_count].scan_32.data, 0, 32);
-
- } else {
- if (ejtag_ctrl & EJTAG_CTRL_PRNW) {
- LOG_ERROR("Not a fetch/read access, count: %d", scan_count);
- retval = ERROR_FAIL;
- goto exit;
- }
- if (addr != fetch_addr) {
- LOG_ERROR("Fetch addr mismatch, read: %" PRIx32 " expected: %" PRIx32 " count: %d",
- addr, fetch_addr, scan_count);
- retval = ERROR_FAIL;
- goto exit;
- }
- fetch_addr += 4;
+ scan_count++;
}
- scan_count++;
}
exit:
free(scan_in);
int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
{
- struct pracc_queue_info ctx = {.max_code = 8};
+ struct pracc_queue_info ctx;
pracc_queue_init(&ctx);
- if (ctx.retval != ERROR_OK)
- goto exit;
pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16((addr + 0x8000)))); /* load $8 with modified upper address */
pracc_add(&ctx, 0, MIPS32_LW(8, LOWER16(addr), 8)); /* lw $8, LOWER16(addr)($8) */
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* sw $8,PRACC_OUT_OFFSET($15) */
- pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 of $8 */
- pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 of $8 */
+ pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */
pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, buf);
-exit:
pracc_queue_free(&ctx);
return ctx.retval;
}
return mips32_pracc_read_u32(ejtag_info, addr, (uint32_t *)buf);
uint32_t *data = NULL;
- struct pracc_queue_info ctx = {.max_code = 256 * 3 + 8 + 1}; /* alloc memory for the worst case */
+ struct pracc_queue_info ctx;
pracc_queue_init(&ctx);
- if (ctx.retval != ERROR_OK)
- goto exit;
if (size != 4) {
data = malloc(256 * sizeof(uint32_t));
MIPS32_SW(8, PRACC_OUT_OFFSET + i * 4, 15)); /* store $8 at param out */
addr += size;
}
- pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of reg 8 */
- pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of reg 8 */
- pracc_add(&ctx, 0, MIPS32_LUI(9, UPPER16(ejtag_info->reg9))); /* restore upper 16 bits of reg 9 */
- pracc_add(&ctx, 0, MIPS32_ORI(9, 9, LOWER16(ejtag_info->reg9))); /* restore lower 16 bits of reg 9 */
+ pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */
+ pracc_add_li32(&ctx, 9, ejtag_info->reg9, 0); /* restore $9 */
pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel)
{
- struct pracc_queue_info ctx = {.max_code = 7};
+ struct pracc_queue_info ctx;
pracc_queue_init(&ctx);
- if (ctx.retval != ERROR_OK)
- goto exit;
pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
pracc_add(&ctx, 0, MIPS32_MFC0(8, cp0_reg, cp0_sel)); /* move cp0 reg / sel to $8 */
pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val);
-exit:
pracc_queue_free(&ctx);
return ctx.retval;
}
int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
{
- struct pracc_queue_info ctx = {.max_code = 6};
+ struct pracc_queue_info ctx;
pracc_queue_init(&ctx);
- if (ctx.retval != ERROR_OK)
- goto exit;
- pracc_add(&ctx, 0, MIPS32_LUI(15, UPPER16(val))); /* Load val to $15 */
- pracc_add(&ctx, 0, MIPS32_ORI(15, 15, LOWER16(val)));
+ pracc_add_li32(&ctx, 15, val, 0); /* Load val to $15 */
pracc_add(&ctx, 0, MIPS32_MTC0(15, cp0_reg, cp0_sel)); /* write $15 to cp0 reg / sel */
-
pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
-exit:
pracc_queue_free(&ctx);
return ctx.retval;
}
static int mips32_pracc_synchronize_cache(struct mips_ejtag *ejtag_info,
uint32_t start_addr, uint32_t end_addr, int cached, int rel)
{
- struct pracc_queue_info ctx = {.max_code = 256 * 2 + 5};
+ struct pracc_queue_info ctx;
pracc_queue_init(&ctx);
- if (ctx.retval != ERROR_OK)
- goto exit;
+
/** Find cache line size in bytes */
uint32_t clsiz;
if (rel) { /* Release 2 (rel = 1) */
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
- pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
- pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
+ pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */
+
pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
static int mips32_pracc_write_mem_generic(struct mips_ejtag *ejtag_info,
uint32_t addr, int size, int count, const void *buf)
{
- struct pracc_queue_info ctx = {.max_code = 128 * 3 + 5 + 1}; /* alloc memory for the worst case */
+ struct pracc_queue_info ctx;
pracc_queue_init(&ctx);
- if (ctx.retval != ERROR_OK)
- goto exit;
const uint32_t *buf32 = buf;
const uint16_t *buf16 = buf;
last_upper_base_addr = upper_base_addr;
}
- if (size == 4) { /* for word writes check if one half word is 0 and load it accordingly */
- if (LOWER16(*buf32) == 0)
- pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(*buf32))); /* load only upper value */
- else if (UPPER16(*buf32) == 0)
- pracc_add(&ctx, 0, MIPS32_ORI(8, 0, LOWER16(*buf32))); /* load only lower */
- else {
- pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(*buf32))); /* load upper and lower */
- pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(*buf32)));
- }
+ if (size == 4) {
+ pracc_add_li32(&ctx, 8, *buf32, 1); /* load with li32, optimize */
pracc_add(&ctx, 0, MIPS32_SW(8, LOWER16(addr), 15)); /* store word to memory */
buf32++;
addr += size;
}
- pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of reg 8 */
- pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of reg 8 */
+ pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */
pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
MIPS32_MTC0(1, 24, 0), /* move $1 to depc (pc) */
};
- struct pracc_queue_info ctx = {.max_code = 37 * 2 + 7 + 1};
+ struct pracc_queue_info ctx;
pracc_queue_init(&ctx);
- if (ctx.retval != ERROR_OK)
- goto exit;
- /* load registers 2 to 31 with lui and ori instructions, check if some instructions can be saved */
- for (int i = 2; i < 32; i++) {
- if (LOWER16((regs[i])) == 0) /* if lower half word is 0, lui instruction only */
- pracc_add(&ctx, 0, MIPS32_LUI(i, UPPER16((regs[i]))));
- else if (UPPER16((regs[i])) == 0) /* if upper half word is 0, ori with $0 only*/
- pracc_add(&ctx, 0, MIPS32_ORI(i, 0, LOWER16((regs[i]))));
- else { /* default, load with lui and ori instructions */
- pracc_add(&ctx, 0, MIPS32_LUI(i, UPPER16((regs[i]))));
- pracc_add(&ctx, 0, MIPS32_ORI(i, i, LOWER16((regs[i]))));
- }
- }
+ /* load registers 2 to 31 with li32, optimize */
+ for (int i = 2; i < 32; i++)
+ pracc_add_li32(&ctx, i, regs[i], 1);
for (int i = 0; i != 6; i++) {
- pracc_add(&ctx, 0, MIPS32_LUI(1, UPPER16((regs[i + 32])))); /* load CPO value in $1, with lui and ori */
- pracc_add(&ctx, 0, MIPS32_ORI(1, 1, LOWER16((regs[i + 32]))));
- pracc_add(&ctx, 0, cp0_write_code[i]); /* write value from $1 to CPO register */
+ pracc_add_li32(&ctx, 1, regs[i + 32], 0); /* load CPO value in $1 */
+ pracc_add(&ctx, 0, cp0_write_code[i]); /* write value from $1 to CPO register */
}
pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* load $15 in DeSave */
pracc_add(&ctx, 0, MIPS32_LUI(1, UPPER16((regs[1])))); /* load upper half word in $1 */
- pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
pracc_add(&ctx, 0, MIPS32_ORI(1, 1, LOWER16((regs[1])))); /* load lower half word in $1 */
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
ejtag_info->reg8 = regs[8];
ejtag_info->reg9 = regs[9];
-exit:
pracc_queue_free(&ctx);
return ctx.retval;
}
MIPS32_MFC0(8, 24, 0), /* move depc (pc) to $8 */
};
- struct pracc_queue_info ctx = {.max_code = 49};
+ struct pracc_queue_info ctx;
pracc_queue_init(&ctx);
- if (ctx.retval != ERROR_OK)
- goto exit;
pracc_add(&ctx, 0, MIPS32_MTC0(1, 31, 0)); /* move $1 to COP0 DeSave */
pracc_add(&ctx, 0, MIPS32_LUI(1, PRACC_UPPER_BASE_ADDR)); /* $1 = MIP32_PRACC_BASE_ADDR */
ejtag_info->reg8 = regs[8]; /* reg8 is saved but not restored, next called function should restore it */
ejtag_info->reg9 = regs[9];
-exit:
pracc_queue_free(&ctx);
return ctx.retval;
}
int write_t, uint32_t addr, int count, uint32_t *buf)
{
uint32_t handler_code[] = {
- /* caution when editing, table is modified below */
/* r15 points to the start of this code */
MIPS32_SW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15),
MIPS32_SW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15),
/* start of fastdata area in t0 */
MIPS32_LUI(8, UPPER16(MIPS32_PRACC_FASTDATA_AREA)),
MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_FASTDATA_AREA)),
- MIPS32_LW(9, 0, 8), /* start addr in t1 */
- MIPS32_LW(10, 0, 8), /* end addr to t2 */
- /* loop: */
- /* 8 */ MIPS32_LW(11, 0, 0), /* lw t3,[t8 | r9] */
- /* 9 */ MIPS32_SW(11, 0, 0), /* sw t3,[r9 | r8] */
- MIPS32_BNE(10, 9, NEG16(3)), /* bne $t2,t1,loop */
- MIPS32_ADDI(9, 9, 4), /* addi t1,t1,4 */
+ MIPS32_LW(9, 0, 8), /* start addr in t1 */
+ MIPS32_LW(10, 0, 8), /* end addr to t2 */
+ /* loop: */
+ write_t ? MIPS32_LW(11, 0, 8) : MIPS32_LW(11, 0, 9), /* from xfer area : from memory */
+ write_t ? MIPS32_SW(11, 0, 9) : MIPS32_SW(11, 0, 8), /* to memory : to xfer area */
+
+ MIPS32_BNE(10, 9, NEG16(3)), /* bne $t2,t1,loop */
+ MIPS32_ADDI(9, 9, 4), /* addi t1,t1,4 */
MIPS32_LW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15),
MIPS32_LW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15),
MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
};
- uint32_t jmp_code[] = {
- /* 0 */ MIPS32_LUI(15, 0), /* addr of working area added below */
- /* 1 */ MIPS32_ORI(15, 15, 0), /* addr of working area added below */
- MIPS32_JR(15), /* jump to ram program */
- MIPS32_NOP,
- };
-
- int retval, i;
- uint32_t val, ejtag_ctrl;
-
if (source->size < MIPS32_FASTDATA_HANDLER_SIZE)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- if (write_t) {
- handler_code[8] = MIPS32_LW(11, 0, 8); /* load data from probe at fastdata area */
- handler_code[9] = MIPS32_SW(11, 0, 9); /* store data to RAM @ r9 */
- } else {
- handler_code[8] = MIPS32_LW(11, 0, 9); /* load data from RAM @ r9 */
- handler_code[9] = MIPS32_SW(11, 0, 8); /* store data to probe at fastdata area */
- }
-
- /* write program into RAM */
+ /* write program into RAM */
if (write_t != ejtag_info->fast_access_save) {
mips32_pracc_write_mem(ejtag_info, source->address, 4, ARRAY_SIZE(handler_code), handler_code);
/* save previous operation to speed to any consecutive read/writes */
LOG_DEBUG("%s using 0x%.8" TARGET_PRIxADDR " for write handler", __func__, source->address);
- jmp_code[0] |= UPPER16(source->address);
- jmp_code[1] |= LOWER16(source->address);
+ uint32_t jmp_code[] = {
+ MIPS32_LUI(15, UPPER16(source->address)), /* load addr of jump in $15 */
+ MIPS32_ORI(15, 15, LOWER16(source->address)),
+ MIPS32_JR(15), /* jump to ram program */
+ MIPS32_NOP,
+ };
- for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++) {
- retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
+ /* execute jump code, with no address check */
+ for (unsigned i = 0; i < ARRAY_SIZE(jmp_code); i++) {
+ int retval = wait_for_pracc_rw(ejtag_info);
if (retval != ERROR_OK)
return retval;
mips_ejtag_drscan_32_out(ejtag_info, jmp_code[i]);
/* Clear the access pending bit (let the processor eat!) */
- ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
- mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
+ mips32_pracc_finish(ejtag_info);
}
/* wait PrAcc pending bit for FASTDATA write, read address */
- retval = mips32_pracc_read_ctrl_addr(ejtag_info);
+ int retval = mips32_pracc_read_ctrl_addr(ejtag_info);
if (retval != ERROR_OK)
return retval;
return ERROR_FAIL;
/* Send the load start address */
- val = addr;
+ uint32_t val = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
- retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
+ retval = wait_for_pracc_rw(ejtag_info);
if (retval != ERROR_OK)
return retval;
if (ejtag_info->mode != 0)
num_clocks = ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000;
- for (i = 0; i < count; i++) {
+ for (int i = 0; i < count; i++) {
jtag_add_clocks(num_clocks);
- retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++);
- if (retval != ERROR_OK)
- return retval;
+ mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++);
}
retval = jtag_execute_queue();
Code Review / openocd.git / blobdiff