+void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
+{
+ struct jtag_tap *tap;
+ tap = ejtag_info->tap;
+ assert(tap != NULL);
+
+ struct scan_field field;
+
+ field.num_bits = 8;
+ field.out_value = &data;
+ field.in_value = NULL;
+
+ jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
+}
+
+/* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
+int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
+{
+ struct pracc_queue_info ctx = {.max_code = 7};
+ pracc_queue_init(&ctx);
+ if (ctx.retval != ERROR_OK)
+ goto exit;
+
+ pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
+ pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
+ if (!enable_step)
+ pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
+
+ pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
+ pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
+ pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1)))); /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
+exit:
+ pracc_queue_free(&ctx);
+ return ctx.retval;
+}
+
+/*
+ * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
+ * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
+ * For example bcm7401 and others. At leas on some
+ * CPUs, DebugMode wont start if this bit is not removed.
+ */
+static int disable_dcr_mp(struct mips_ejtag *ejtag_info)