+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2008 by David T.L. Wong *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef OPENOCD_TARGET_MIPS_EJTAG_H
/* v2.0 - 1:4 Number of Break Channels. */
#define EJTAG_V20_IMP_BCHANNELS_MASK 0xf
#define EJTAG_V20_IMP_BCHANNELS_SHIFT 1
-#define EJTAG_DCR_MIPS64 (1 << 0)
+#define EJTAG_IMP_MIPS64 (1 << 0)
/* Debug Control Register DCR */
#define EJTAG_DCR 0xFF300000
-#define EJTAG_DCR_ENM (1 << 29)
-#define EJTAG_DCR_DB (1 << 17)
-#define EJTAG_DCR_IB (1 << 16)
-#define EJTAG_DCR_INTE (1 << 4)
-#define EJTAG_DCR_MP (1 << 2)
+#define EJTAG_DCR_ENM BIT(29)
+#define EJTAG_DCR_FDC BIT(18)
+#define EJTAG_DCR_DB BIT(17)
+#define EJTAG_DCR_IB BIT(16)
+#define EJTAG_DCR_INTE BIT(4)
+#define EJTAG_DCR_MP BIT(2)
/* breakpoint support */
/* EJTAG_V20_* was tested on Broadcom BCM7401
#define EJTAG_V20_IBA0 0xFF300100
#define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */
#define EJTAG_V20_IBM_OFFS 0x8
-#define EJTAG_V20_IBAn_STEP 0x10 /* Offset for next channel */
+#define EJTAG_V20_IBAN_STEP 0x10 /* Offset for next channel */
#define EJTAG_V20_DBS 0xFF300008
#define EJTAG_V20_DBA0 0xFF300200
#define EJTAG_V20_DBC_OFFS 0x4
#define EJTAG_V20_DBM_OFFS 0x8
#define EJTAG_V20_DBV_OFFS 0xc
-#define EJTAG_V20_DBAn_STEP 0x10
+#define EJTAG_V20_DBAN_STEP 0x10
#define EJTAG_V25_IBS 0xFF301000
#define EJTAG_V25_IBA0 0xFF301100
#define EJTAG_V25_IBM_OFFS 0x8
#define EJTAG_V25_IBASID_OFFS 0x10
#define EJTAG_V25_IBC_OFFS 0x18
-#define EJTAG_V25_IBAn_STEP 0x100
+#define EJTAG_V25_IBAN_STEP 0x100
#define EJTAG_V25_DBS 0xFF302000
#define EJTAG_V25_DBA0 0xFF302100
#define EJTAG_V25_DBM_OFFS 0x8
#define EJTAG_V25_DBASID_OFFS 0x10
#define EJTAG_V25_DBC_OFFS 0x18
#define EJTAG_V25_DBV_OFFS 0x20
-#define EJTAG_V25_DBAn_STEP 0x100
+#define EJTAG_V25_DBAN_STEP 0x100
-#define EJTAG_DBCn_NOSB (1 << 13)
-#define EJTAG_DBCn_NOLB (1 << 12)
-#define EJTAG_DBCn_BLM_MASK 0xff
-#define EJTAG_DBCn_BLM_SHIFT 4
-#define EJTAG_DBCn_BE (1 << 0)
+#define EJTAG_DBCN_NOSB (1 << 13)
+#define EJTAG_DBCN_NOLB (1 << 12)
+#define EJTAG_DBCN_BLM_MASK 0xff
+#define EJTAG_DBCN_BLM_SHIFT 4
+#define EJTAG_DBCN_BE (1 << 0)
#define EJTAG_VERSION_20 0
#define EJTAG_VERSION_25 1
#define EJTAG_VERSION_41 4
#define EJTAG_VERSION_51 5
+/*
+ * Additional defines for MIPS64 EJTAG
+ */
+#define EJTAG64_DCR 0xFFFFFFFFFF300000ull
+#define EJTAG64_DCR_ENM (1llu << 29)
+#define EJTAG64_DCR_DB (1llu << 17)
+#define EJTAG64_DCR_IB (1llu << 16)
+#define EJTAG64_DCR_INTE (1llu << 4)
+#define EJTAG64_DCR_MP (1llu << 2)
+#define EJTAG64_V25_DBA0 0xFFFFFFFFFF302100ull
+#define EJTAG64_V25_DBS 0xFFFFFFFFFF302000ull
+#define EJTAG64_V25_IBA0 0xFFFFFFFFFF301100ull
+#define EJTAG64_V25_IBS 0xFFFFFFFFFF301000ull
+
+static const struct dcr_feature {
+ int bit;
+ const char *name;
+} dcr_features[] = {
+ {22, "DAS"},
+ {18, "FDC"},
+ {17, "DataBrk"},
+ {16, "InstBrk"},
+ {15, "Inverted Data value"},
+ {14, "Data value stored"},
+ {10, "Complex Breakpoints"},
+ { 9, "PC Sampling"},
+};
+
+#define EJTAG_DCR_ENTRIES (ARRAY_SIZE(dcr_features))
+
struct mips_ejtag {
struct jtag_tap *tap;
uint32_t impcode;
uint32_t idcode;
+ uint32_t prid;
uint32_t ejtag_ctrl;
int fast_access_save;
uint32_t config_regs; /* number of config registers read */
void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr);
int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
+int mips64_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info);
void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
+int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data);
void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data);
int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
+int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint64_t *data);
int mips_ejtag_init(struct mips_ejtag *ejtag_info);
int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
+int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step);
+
+void ejtag_main_print_imp(struct mips_ejtag *ejtag_info);
+int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info);
static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
{
*((uint32_t *)arg) = le_to_h_u32(in);
}
+static inline void mips_le_to_h_u64(jtag_callback_data_t arg)
+{
+ uint8_t *in = (uint8_t *)arg;
+ *((uint64_t *)arg) = le_to_h_u64(in);
+}
+
#endif /* OPENOCD_TARGET_MIPS_EJTAG_H */
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