Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
mips_m4k.c: EJTAGBOOT and NORMALBOOT are not supported on EJTAG 2.0
[openocd.git] / src / target / mips_m4k.c
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 49edad184a1d32e01b3bfdcc4be727805f5423ef..5b740cc45242b614800d4e66a11fc4cc73467cb8 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -57,33 +57,37 @@ static int mips_m4k_examine_debug_reason(struct target *target)
        int retval;
 
        if ((target->debug_reason != DBG_REASON_DBGRQ)
-               && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
-               /* get info about inst breakpoint support */
-               retval = target_read_u32(target,
-                       ejtag_info->ejtag_ibs_addr, &break_status);
-               if (retval != ERROR_OK)
-                       return retval;
-               if (break_status & 0x1f) {
-                       /* we have halted on a  breakpoint */
-                       retval = target_write_u32(target,
-                               ejtag_info->ejtag_ibs_addr, 0);
+                       && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
+               if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
+                       /* get info about inst breakpoint support */
+                       retval = target_read_u32(target,
+                               ejtag_info->ejtag_ibs_addr, &break_status);
                        if (retval != ERROR_OK)
                                return retval;
-                       target->debug_reason = DBG_REASON_BREAKPOINT;
+                       if (break_status & 0x1f) {
+                               /* we have halted on a  breakpoint */
+                               retval = target_write_u32(target,
+                                       ejtag_info->ejtag_ibs_addr, 0);
+                               if (retval != ERROR_OK)
+                                       return retval;
+                               target->debug_reason = DBG_REASON_BREAKPOINT;
+                       }
                }
 
-               /* get info about data breakpoint support */
-               retval = target_read_u32(target,
-                       ejtag_info->ejtag_dbs_addr, &break_status);
-               if (retval != ERROR_OK)
-                       return retval;
-               if (break_status & 0x1f) {
-                       /* we have halted on a  breakpoint */
-                       retval = target_write_u32(target,
-                               ejtag_info->ejtag_dbs_addr, 0);
+               if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
+                       /* get info about data breakpoint support */
+                       retval = target_read_u32(target,
+                               ejtag_info->ejtag_dbs_addr, &break_status);
                        if (retval != ERROR_OK)
                                return retval;
-                       target->debug_reason = DBG_REASON_WATCHPOINT;
+                       if (break_status & 0x1f) {
+                               /* we have halted on a  breakpoint */
+                               retval = target_write_u32(target,
+                                       ejtag_info->ejtag_dbs_addr, 0);
+                               if (retval != ERROR_OK)
+                                       return retval;
+                               target->debug_reason = DBG_REASON_WATCHPOINT;
+                       }
                }
        }
 
@@ -147,7 +151,7 @@ static int mips_m4k_halt_smp(struct target *target)
                        ret = mips_m4k_halt(curr);
 
                if (ret != ERROR_OK) {
-                       LOG_ERROR("halt failed target->coreid: %d", curr->coreid);
+                       LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
                        retval = ret;
                }
                head = head->next;
@@ -314,11 +318,15 @@ static int mips_m4k_assert_reset(struct target *target)
                srst_asserted = true;
        }
 
-       if (target->reset_halt) {
-               /* use hardware to catch reset */
-               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
-       } else
-               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
+
+       /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
+       if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
+               if (target->reset_halt) {
+                       /* use hardware to catch reset */
+                       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
+               } else
+                       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
+       }
 
        if (jtag_reset_config & RESET_HAS_SRST) {
                /* here we should issue a srst only, but we may have to assert trst as well */
@@ -370,12 +378,6 @@ static int mips_m4k_deassert_reset(struct target *target)
        return ERROR_OK;
 }
 
-static int mips_m4k_soft_reset_halt(struct target *target)
-{
-       /* TODO */
-       return ERROR_OK;
-}
-
 static int mips_m4k_single_step_core(struct target *target)
 {
        struct mips32_common *mips32 = target_to_mips32(target);
@@ -411,7 +413,7 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han
                                                   handle_breakpoints, 0);
 
                        if (ret != ERROR_OK) {
-                               LOG_ERROR("target->coreid :%d failed to resume at address :0x%x",
+                               LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
                                                  curr->coreid, address);
                                retval = ret;
                        }
@@ -608,7 +610,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
                while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
                        bp_num++;
                if (bp_num >= mips32->num_inst_bpoints) {
-                       LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
+                       LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
                                        breakpoint->unique_id);
                        return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
                }
@@ -628,11 +630,11 @@ static int mips_m4k_set_breakpoint(struct target *target,
                                 ejtag_info->ejtag_ibm_offs, 0x00000000);
                target_write_u32(target, comparator_list[bp_num].reg_address +
                                 ejtag_info->ejtag_ibc_offs, 1);
-               LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
+               LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
                                  breakpoint->unique_id,
                                  bp_num, comparator_list[bp_num].bp_value);
        } else if (breakpoint->type == BKPT_SOFT) {
-               LOG_DEBUG("bpid: %d", breakpoint->unique_id);
+               LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
                if (breakpoint->length == 4) {
                        uint32_t verify = 0xffffffff;
 
@@ -696,11 +698,11 @@ static int mips_m4k_unset_breakpoint(struct target *target,
        if (breakpoint->type == BKPT_HARD) {
                int bp_num = breakpoint->set - 1;
                if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
-                       LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
+                       LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
                                          breakpoint->unique_id);
                        return ERROR_OK;
                }
-               LOG_DEBUG("bpid: %d - releasing hw: %d",
+               LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
                                breakpoint->unique_id,
                                bp_num);
                comparator_list[bp_num].used = 0;
@@ -710,7 +712,7 @@ static int mips_m4k_unset_breakpoint(struct target *target,
 
        } else {
                /* restore original instruction (kept in target endianness) */
-               LOG_DEBUG("bpid: %d", breakpoint->unique_id);
+               LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
                if (breakpoint->length == 4) {
                        uint32_t current_instr;
 
@@ -1054,9 +1056,9 @@ static int mips_m4k_write_memory(struct target *target, uint32_t address,
        /* if noDMA off, use DMAACC mode for memory write */
        int retval;
        if (ejtag_info->impcode & EJTAG_IMP_NODMA)
-               retval = mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+               retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
        else
-               retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+               retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
 
        if (t != NULL)
                free(t);
@@ -1137,6 +1139,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
 {
        struct mips32_common *mips32 = target_to_mips32(target);
        struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+       struct working_area *fast_data_area;
        int retval;
        int write_t = 1;
 
@@ -1163,6 +1166,17 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
                ejtag_info->fast_access_save = -1;
        }
 
+       fast_data_area = mips32->fast_data_area;
+
+       if (address <= fast_data_area->address + fast_data_area->size &&
+                       fast_data_area->address <= address + count) {
+               LOG_ERROR("fast_data (0x%8.8" PRIx32 ") is within write area "
+                         "(0x%8.8" PRIx32 "-0x%8.8" PRIx32 ").",
+                         fast_data_area->address, address, address + count);
+               LOG_ERROR("Change work-area-phys or load_image address!");
+               return ERROR_FAIL;
+       }
+
        /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
        /* but byte array represents target endianness                      */
        uint32_t *t = NULL;
@@ -1302,7 +1316,7 @@ COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
                        target->gdb_service->core[1] = coreid;
 
                }
-               command_print(CMD_CTX, "gdb coreid  %d -> %d", target->gdb_service->core[0]
+               command_print(CMD_CTX, "gdb coreid  %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
                        , target->gdb_service->core[1]);
        }
        return ERROR_OK;
@@ -1315,7 +1329,7 @@ COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
        struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 
        if (CMD_ARGC == 1)
-               COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], ejtag_info->scan_delay);
+               COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
        else if (CMD_ARGC > 1)
                        return ERROR_COMMAND_SYNTAX_ERROR;
 
@@ -1390,15 +1404,12 @@ struct target_type mips_m4k_target = {
        .poll = mips_m4k_poll,
        .arch_state = mips32_arch_state,
 
-       .target_request_data = NULL,
-
        .halt = mips_m4k_halt,
        .resume = mips_m4k_resume,
        .step = mips_m4k_step,
 
        .assert_reset = mips_m4k_assert_reset,
        .deassert_reset = mips_m4k_deassert_reset,
-       .soft_reset_halt = mips_m4k_soft_reset_halt,
 
        .get_gdb_reg_list = mips32_get_gdb_reg_list,
 
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)