jtag_add_reset(1, 1);
else if (!srst_asserted)
jtag_add_reset(0, 1);
+ } else if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
} else {
if (mips_m4k->is_pic32mx) {
LOG_DEBUG("Using MTAP reset to reset processor...");
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
- mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
- mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
+ mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
+ mips32->core_cache->reg_list[MIPS32_PC].valid = true;
}
if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
- mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
- mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
+ mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
+ mips32->core_cache->reg_list[MIPS32_PC].valid = true;
}
/* the front-end may request us not to handle breakpoints */
}
if (verify == 0) {
- LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx64
+ LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}
return retval;
if (verify != MIPS16_SDBBP(isa_req)) {
- LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx64
+ LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}