mips: code clean up in mips_m4k_debug_entry() function

[openocd.git] / src / target / mips_m4k.c

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 623d55e0d8360e9dcabc25cf010324f8f34ae1a4..9a3d929c8c1d01fde3bbcb25727659978f0b5b5e 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -82,10 +82,9 @@ static int mips_m4k_debug_entry(struct target *target)
 {
        struct mips32_common *mips32 = target_to_mips32(target);
        struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
-       uint32_t debug_reg;
 
-       /* read debug register */
-       mips_ejtag_read_debug(ejtag_info, &debug_reg);
+       /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
+       mips_ejtag_config_step(ejtag_info, 0);
 
        /* make sure break unit configured */
        mips32_configure_break_unit(target);
@@ -93,12 +92,6 @@ static int mips_m4k_debug_entry(struct target *target)
        /* attempt to find halt reason */
        mips_m4k_examine_debug_reason(target);
 
-       /* clear single step if active */
-       if (debug_reg & EJTAG_DEBUG_DSS) {
-               /* stopped due to single step - clear step bit */
-               mips_ejtag_config_step(ejtag_info, 0);
-       }
-
        mips32_save_context(target);
 
        /* default to mips32 isa, it will be changed below if required */
@@ -143,6 +136,17 @@ static int mips_m4k_poll(struct target *target)
 
        /* check for processor halted */
        if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
+               if (target->state == TARGET_UNKNOWN) {
+                       LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
+
+                       /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
+                        * (maybe put on by HALT-ing the board in the previous session).
+                        *
+                        * Force target to RUNNING state to enable debug entry for this session.
+                        */
+                       target->state = TARGET_RUNNING;
+               }
+
                if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
                        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 
@@ -211,15 +215,22 @@ static int mips_m4k_assert_reset(struct target *target)
 {
        struct mips_m4k_common *mips_m4k = target_to_m4k(target);
        struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
-       int assert_srst = 1;
 
        LOG_DEBUG("target->state: %s",
                target_state_name(target));
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();
 
-       if (!(jtag_reset_config & RESET_HAS_SRST))
-               assert_srst = 0;
+       /* some cores support connecting while srst is asserted
+        * use that mode is it has been configured */
+
+       bool srst_asserted = false;
+
+       if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
+                       (jtag_reset_config & RESET_SRST_NO_GATING)) {
+               jtag_add_reset(0, 1);
+               srst_asserted = true;
+       }
 
        if (target->reset_halt) {
                /* use hardware to catch reset */
@@ -227,11 +238,11 @@ static int mips_m4k_assert_reset(struct target *target)
        } else
                mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 
-       if (assert_srst) {
+       if (jtag_reset_config & RESET_HAS_SRST) {
                /* here we should issue a srst only, but we may have to assert trst as well */
                if (jtag_reset_config & RESET_SRST_PULLS_TRST)
                        jtag_add_reset(1, 1);
-               else
+               else if (!srst_asserted)
                        jtag_add_reset(0, 1);
        } else {
                if (mips_m4k->is_pic32mx) {