#include "mips32_dmaacc.h"
#include "target_type.h"
#include "register.h"
+#include "smp.h"
static void mips_m4k_enable_breakpoints(struct target *target);
static void mips_m4k_enable_watchpoints(struct target *target);
/* the next polling trigger an halt event sent to gdb */
if ((target->state == TARGET_HALTED) && (target->smp) &&
(target->gdb_service) &&
- (target->gdb_service->target == NULL)) {
+ (!target->gdb_service->target)) {
target->gdb_service->target =
get_mips_m4k(target, target->gdb_service->core[1]);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
jtag_add_reset(1, 1);
else if (!srst_asserted)
jtag_add_reset(0, 1);
+ } else if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
} else {
if (mips_m4k->is_pic32mx) {
LOG_DEBUG("Using MTAP reset to reset processor...");
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
- mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
- mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
+ mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
+ mips32->core_cache->reg_list[MIPS32_PC].valid = true;
}
if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
- mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
- mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
+ mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
+ mips32->core_cache->reg_list[MIPS32_PC].valid = true;
}
/* the front-end may request us not to handle breakpoints */
if (ejtag_info->endianness && isa_req)
sdbbp32_instr = SWAP16(sdbbp32_instr);
- if ((breakpoint->address & 3) == 0) { /* word alligned */
+ if ((breakpoint->address & 3) == 0) { /* word aligned */
retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
if (retval != ERROR_OK)
}
if (verify == 0) {
- LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx64
+ LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}
return retval;
if (verify != MIPS16_SDBBP(isa_req)) {
- LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx64
+ LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}
if (retval != ERROR_OK)
return retval;
/**
- * target_read_memory() gets us data in _target_ endianess.
+ * target_read_memory() gets us data in _target_ endianness.
* If we want to use this data on the host for comparisons with some macros
- * we must first transform it to _host_ endianess using target_buffer_get_u16().
+ * we must first transform it to _host_ endianness using target_buffer_get_u16().
*/
if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
retval = target_write_memory(target, breakpoint->address, 4, 1,
if (retval != ERROR_OK)
return retval;
}
- } else { /* 16bit alligned */
+ } else { /* 16bit aligned */
retval = target_read_memory(target, breakpoint->address, 2, 2, current_instr);
if (retval != ERROR_OK)
return retval;
* and exclude both load and store accesses from watchpoint
* condition evaluation
*/
- int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
- (0xff << EJTAG_DBCn_BLM_SHIFT);
+ int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |
+ (0xff << EJTAG_DBCN_BLM_SHIFT);
if (watchpoint->set) {
LOG_WARNING("watchpoint already set");
switch (watchpoint->rw) {
case WPT_READ:
- enable &= ~EJTAG_DBCn_NOLB;
+ enable &= ~EJTAG_DBCN_NOLB;
break;
case WPT_WRITE:
- enable &= ~EJTAG_DBCn_NOSB;
+ enable &= ~EJTAG_DBCN_NOSB;
break;
case WPT_ACCESS:
- enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
+ enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
break;
default:
LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
if (size > 1) {
t = malloc(count * size * sizeof(uint8_t));
- if (t == NULL) {
+ if (!t) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
/* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
/* endianness, but byte array should represent target endianness */
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
switch (size) {
case 4:
target_buffer_set_u32_array(target, buffer, count, t);
}
}
- if ((size > 1) && (t != NULL))
+ if (size > 1)
free(t);
return retval;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
- /** correct endianess if we have word or hword access */
+ /** correct endianness if we have word or hword access */
void *t = NULL;
if (size > 1) {
/* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
/* endianness, but byte array represents target endianness */
t = malloc(count * size * sizeof(uint8_t));
- if (t == NULL) {
+ if (!t) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
else
retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
- if (t != NULL)
- free(t);
+ free(t);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
return ERROR_OK;
static int mips_m4k_examine(struct target *target)
{
- int retval;
struct mips_m4k_common *mips_m4k = target_to_m4k(target);
struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
- uint32_t idcode = 0;
if (!target_was_examined(target)) {
- retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
- if (retval != ERROR_OK)
+ int retval = mips_ejtag_get_idcode(ejtag_info);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("idcode read failed");
return retval;
- ejtag_info->idcode = idcode;
-
- if (((idcode >> 1) & 0x7FF) == 0x29) {
+ }
+ if (((ejtag_info->idcode >> 1) & 0x7FF) == 0x29) {
/* we are using a pic32mx so select ejtag port
* as it is not selected by default */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
- LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
+ LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
mips_m4k->is_pic32mx = true;
}
}
/* init rest of ejtag interface */
- retval = mips_ejtag_init(ejtag_info);
+ int retval = mips_ejtag_init(ejtag_info);
if (retval != ERROR_OK)
return retval;
- retval = mips32_examine(target);
- if (retval != ERROR_OK)
- return retval;
-
- return ERROR_OK;
+ return mips32_examine(target);
}
static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
if (address & 0x3u)
return ERROR_TARGET_UNALIGNED_ACCESS;
- if (mips32->fast_data_area == NULL) {
+ if (!mips32->fast_data_area) {
/* Get memory for block write handler
* we preserve this area between calls and gain a speed increase
* of about 3kb/sec when writing flash
/* but byte array represents target endianness */
uint32_t *t = NULL;
t = malloc(count * sizeof(uint32_t));
- if (t == NULL) {
+ if (!t) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
count, t);
- if (t != NULL)
- free(t);
+ free(t);
if (retval != ERROR_OK)
LOG_ERROR("Fastdata access Failed");
return retval;
}
-static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
+static int mips_m4k_verify_pointer(struct command_invocation *cmd,
struct mips_m4k_common *mips_m4k)
{
if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
- command_print(cmd_ctx, "target is not an MIPS_M4K");
+ command_print(cmd, "target is not an MIPS_M4K");
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
struct mips_m4k_common *mips_m4k = target_to_m4k(target);
struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
- retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
+ retval = mips_m4k_verify_pointer(CMD, mips_m4k);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
- command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
uint32_t value;
retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
if (retval != ERROR_OK) {
- command_print(CMD_CTX,
- "couldn't access reg %" PRIi32,
+ command_print(CMD,
+ "couldn't access reg %" PRIu32,
cp0_reg);
return ERROR_OK;
}
- command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+ command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
cp0_reg, cp0_sel, value);
} else if (CMD_ARGC == 3) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
if (retval != ERROR_OK) {
- command_print(CMD_CTX,
- "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
+ command_print(CMD,
+ "couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
cp0_reg, cp0_sel);
return ERROR_OK;
}
- command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+ command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
cp0_reg, cp0_sel, value);
}
}
return ERROR_OK;
}
-COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
-{
- struct target *target = get_current_target(CMD_CTX);
- /* check target is an smp target */
- struct target_list *head;
- struct target *curr;
- head = target->head;
- target->smp = 0;
- if (head != (struct target_list *)NULL) {
- while (head != (struct target_list *)NULL) {
- curr = head->target;
- curr->smp = 0;
- head = head->next;
- }
- /* fixes the target display to the debugger */
- target->gdb_service->target = target;
- }
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
-{
- struct target *target = get_current_target(CMD_CTX);
- struct target_list *head;
- struct target *curr;
- head = target->head;
- if (head != (struct target_list *)NULL) {
- target->smp = 1;
- while (head != (struct target_list *)NULL) {
- curr = head->target;
- curr->smp = 1;
- head = head->next;
- }
- }
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
-{
- struct target *target = get_current_target(CMD_CTX);
- int retval = ERROR_OK;
- struct target_list *head;
- head = target->head;
- if (head != (struct target_list *)NULL) {
- if (CMD_ARGC == 1) {
- int coreid = 0;
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
- if (ERROR_OK != retval)
- return retval;
- target->gdb_service->core[1] = coreid;
-
- }
- command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
- , target->gdb_service->core[1]);
- }
- return ERROR_OK;
-}
-
COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
{
struct target *target = get_current_target(CMD_CTX);
else if (CMD_ARGC > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
- command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
+ command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
ejtag_info->mode = 0;
- command_print(CMD_CTX, "running in legacy mode");
+ command_print(CMD, "running in legacy mode");
} else {
ejtag_info->mode = 1;
- command_print(CMD_CTX, "running in fast queued mode");
+ command_print(CMD, "running in fast queued mode");
}
return ERROR_OK;
.usage = "regnum [value]",
.help = "display/modify cp0 register",
},
- {
- .name = "smp_off",
- .handler = mips_m4k_handle_smp_off_command,
- .mode = COMMAND_EXEC,
- .help = "Stop smp handling",
- .usage = "",},
-
- {
- .name = "smp_on",
- .handler = mips_m4k_handle_smp_on_command,
- .mode = COMMAND_EXEC,
- .help = "Restart smp handling",
- .usage = "",
- },
- {
- .name = "smp_gdb",
- .handler = mips_m4k_handle_smp_gdb_command,
- .mode = COMMAND_EXEC,
- .help = "display/fix current core played to gdb",
- .usage = "",
- },
{
.name = "scan_delay",
.handler = mips_m4k_handle_scan_delay_command,
.help = "display/set scan delay in nano seconds",
.usage = "[value]",
},
+ {
+ .chain = smp_command_handlers,
+ },
COMMAND_REGISTRATION_DONE
};
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