struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
nds32->step_isr_enable = false;
}
- command_print(CMD_CTX, "%s: $INT_MASK.DSSIM: %d", target_name(target),
+ command_print(CMD, "%s: $INT_MASK.DSSIM: %d", target_name(target),
nds32->step_isr_enable);
return ERROR_OK;
struct nds32_memory *memory = &(nds32->memory);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
aice_memory_access(aice, memory->access_channel);
} else {
- command_print(CMD_CTX, "%s: memory access channel: %s",
+ command_print(CMD, "%s: memory access channel: %s",
target_name(target),
NDS_MEMORY_ACCESS_NAME[memory->access_channel]);
}
struct aice_port_s *aice = target_to_aice(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
if (CMD_ARGC > 0) {
if (nds32->edm.access_control == false) {
- command_print(CMD_CTX, "%s does not support ACC_CTL. "
+ command_print(CMD, "%s does not support ACC_CTL. "
"Set memory mode to MEMORY", target_name(target));
nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
} else if (nds32->edm.direct_access_local_memory == false) {
- command_print(CMD_CTX, "%s does not support direct access "
+ command_print(CMD, "%s does not support direct access "
"local memory. Set memory mode to MEMORY",
target_name(target));
nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
} else if (strcmp(CMD_ARGV[0], "ilm") == 0) {
if (nds32->memory.ilm_base == 0)
- command_print(CMD_CTX, "%s does not support ILM",
+ command_print(CMD, "%s does not support ILM",
target_name(target));
else
nds32->memory.mode = NDS_MEMORY_SELECT_ILM;
} else if (strcmp(CMD_ARGV[0], "dlm") == 0) {
if (nds32->memory.dlm_base == 0)
- command_print(CMD_CTX, "%s does not support DLM",
+ command_print(CMD, "%s does not support DLM",
target_name(target));
else
nds32->memory.mode = NDS_MEMORY_SELECT_DLM;
}
}
- command_print(CMD_CTX, "%s: memory mode: %s",
+ command_print(CMD, "%s: memory mode: %s",
target_name(target),
NDS_MEMORY_SELECT_NAME[nds32->memory.mode]);
int result;
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
/* D$ write back */
result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
if (result != ERROR_OK) {
- command_print(CMD_CTX, "%s: Write back data cache...failed",
+ command_print(CMD, "%s: Write back data cache...failed",
target_name(target));
return result;
}
- command_print(CMD_CTX, "%s: Write back data cache...done",
+ command_print(CMD, "%s: Write back data cache...done",
target_name(target));
/* D$ invalidate */
result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
if (result != ERROR_OK) {
- command_print(CMD_CTX, "%s: Invalidate data cache...failed",
+ command_print(CMD, "%s: Invalidate data cache...failed",
target_name(target));
return result;
}
- command_print(CMD_CTX, "%s: Invalidate data cache...done",
+ command_print(CMD, "%s: Invalidate data cache...done",
target_name(target));
} else {
if (dcache->line_size == 0)
- command_print(CMD_CTX, "%s: No data cache",
+ command_print(CMD, "%s: No data cache",
target_name(target));
else
- command_print(CMD_CTX, "%s: Data cache disabled",
+ command_print(CMD, "%s: Data cache disabled",
target_name(target));
}
/* I$ invalidate */
result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
if (result != ERROR_OK) {
- command_print(CMD_CTX, "%s: Invalidate instruction cache...failed",
+ command_print(CMD, "%s: Invalidate instruction cache...failed",
target_name(target));
return result;
}
- command_print(CMD_CTX, "%s: Invalidate instruction cache...done",
+ command_print(CMD, "%s: Invalidate instruction cache...done",
target_name(target));
} else {
if (icache->line_size == 0)
- command_print(CMD_CTX, "%s: No instruction cache",
+ command_print(CMD, "%s: No instruction cache",
target_name(target));
else
- command_print(CMD_CTX, "%s: Instruction cache disabled",
+ command_print(CMD, "%s: Instruction cache disabled",
target_name(target));
}
} else
- command_print(CMD_CTX, "No valid parameter");
+ command_print(CMD, "No valid parameter");
}
return ERROR_OK;
int result;
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
if (CMD_ARGC > 0) {
if (icache->line_size == 0) {
- command_print(CMD_CTX, "%s: No instruction cache",
+ command_print(CMD, "%s: No instruction cache",
target_name(target));
return ERROR_OK;
}
/* I$ invalidate */
result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
if (result != ERROR_OK) {
- command_print(CMD_CTX, "%s: Invalidate instruction cache...failed",
+ command_print(CMD, "%s: Invalidate instruction cache...failed",
target_name(target));
return result;
}
- command_print(CMD_CTX, "%s: Invalidate instruction cache...done",
+ command_print(CMD, "%s: Invalidate instruction cache...done",
target_name(target));
} else {
- command_print(CMD_CTX, "%s: Instruction cache disabled",
+ command_print(CMD, "%s: Instruction cache disabled",
target_name(target));
}
} else if (strcmp(CMD_ARGV[0], "enable") == 0) {
} else if (strcmp(CMD_ARGV[0], "dump") == 0) {
/* TODO: dump cache content */
} else {
- command_print(CMD_CTX, "%s: No valid parameter", target_name(target));
+ command_print(CMD, "%s: No valid parameter", target_name(target));
}
}
int result;
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
if (CMD_ARGC > 0) {
if (dcache->line_size == 0) {
- command_print(CMD_CTX, "%s: No data cache", target_name(target));
+ command_print(CMD, "%s: No data cache", target_name(target));
return ERROR_OK;
}
/* D$ write back */
result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
if (result != ERROR_OK) {
- command_print(CMD_CTX, "%s: Write back data cache...failed",
+ command_print(CMD, "%s: Write back data cache...failed",
target_name(target));
return result;
}
- command_print(CMD_CTX, "%s: Write back data cache...done",
+ command_print(CMD, "%s: Write back data cache...done",
target_name(target));
/* D$ invalidate */
result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
if (result != ERROR_OK) {
- command_print(CMD_CTX, "%s: Invalidate data cache...failed",
+ command_print(CMD, "%s: Invalidate data cache...failed",
target_name(target));
return result;
}
- command_print(CMD_CTX, "%s: Invalidate data cache...done",
+ command_print(CMD, "%s: Invalidate data cache...done",
target_name(target));
} else {
- command_print(CMD_CTX, "%s: Data cache disabled",
+ command_print(CMD, "%s: Data cache disabled",
target_name(target));
}
} else if (strcmp(CMD_ARGV[0], "enable") == 0) {
} else if (strcmp(CMD_ARGV[0], "dump") == 0) {
/* TODO: dump cache content */
} else {
- command_print(CMD_CTX, "%s: No valid parameter", target_name(target));
+ command_print(CMD, "%s: No valid parameter", target_name(target));
}
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
}
if (nds32->auto_convert_hw_bp)
- command_print(CMD_CTX, "%s: convert sw break to hw break on ROM: on",
+ command_print(CMD, "%s: convert sw break to hw break on ROM: on",
target_name(target));
else
- command_print(CMD_CTX, "%s: convert sw break to hw break on ROM: off",
+ command_print(CMD, "%s: convert sw break to hw break on ROM: off",
target_name(target));
return ERROR_OK;
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
}
if (nds32->virtual_hosting)
- command_print(CMD_CTX, "%s: virtual hosting: on", target_name(target));
+ command_print(CMD, "%s: virtual hosting: on", target_name(target));
else
- command_print(CMD_CTX, "%s: virtual hosting: off", target_name(target));
+ command_print(CMD, "%s: virtual hosting: off", target_name(target));
return ERROR_OK;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
read_addr, &instruction))
return ERROR_FAIL;
- command_print(CMD_CTX, "%s", instruction.text);
+ command_print(CMD, "%s", instruction.text);
read_addr += instruction.instruction_size;
i++;
if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, addr, &instruction))
return ERROR_FAIL;
- command_print(CMD_CTX, "%s", instruction.text);
+ command_print(CMD, "%s", instruction.text);
} else
return ERROR_FAIL;
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
- command_print(CMD_CTX, "OCD");
+ command_print(CMD, "OCD");
return ERROR_OK;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
nds32_get_mapped_reg(nds32, IR0, &value_psw);
if (value_psw & 0x20)
- command_print(CMD_CTX, "%s: BE", target_name(target));
+ command_print(CMD, "%s: BE", target_name(target));
else
- command_print(CMD_CTX, "%s: LE", target_name(target));
+ command_print(CMD, "%s: LE", target_name(target));
return ERROR_OK;
}
struct nds32 *nds32 = target_to_nds32(target);
if (!is_nds32(nds32)) {
- command_print(CMD_CTX, "current target isn't an Andes core");
+ command_print(CMD, "current target isn't an Andes core");
return ERROR_FAIL;
}
- command_print(CMD_CTX, "CPUID: %s", target_name(target));
+ command_print(CMD, "CPUID: %s", target_name(target));
return ERROR_OK;
}