* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include <target/target.h>
#include <target/breakpoints.h>
#include <target/target_type.h>
+#include <helper/time_support.h>
#include <helper/fileio.h>
#include "or1k_tap.h"
#include "or1k.h"
static struct or1k_core_reg *or1k_core_reg_list_arch_info;
-struct or1k_core_reg_init or1k_init_reg_list[] = {
+static const struct or1k_core_reg_init or1k_init_reg_list[] = {
{"r0" , GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
{"r1" , GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
{"r2" , GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
if ((num >= 0) && (num < OR1KNUMCOREREGS)) {
reg_value = or1k->core_regs[num];
buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
- LOG_DEBUG("Read core reg %i value 0x%08x", num , reg_value);
- or1k->core_cache->reg_list[num].valid = 1;
- or1k->core_cache->reg_list[num].dirty = 0;
+ LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value);
+ or1k->core_cache->reg_list[num].valid = true;
+ or1k->core_cache->reg_list[num].dirty = false;
} else {
/* This is an spr, always read value from HW */
int retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
or1k->arch_info[num].spr_num, 1, ®_value);
if (retval != ERROR_OK) {
- LOG_ERROR("Error while reading spr 0x%08x", or1k->arch_info[num].spr_num);
+ LOG_ERROR("Error while reading spr 0x%08" PRIx32, or1k->arch_info[num].spr_num);
return retval;
}
buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
- LOG_DEBUG("Read spr reg %i value 0x%08x", num , reg_value);
+ LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num , reg_value);
}
return ERROR_OK;
uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
or1k->core_regs[num] = reg_value;
- LOG_DEBUG("Write core reg %i value 0x%08x", num , reg_value);
- or1k->core_cache->reg_list[num].valid = 1;
- or1k->core_cache->reg_list[num].dirty = 0;
+ LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value);
+ or1k->core_cache->reg_list[num].valid = true;
+ or1k->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
if (or1k_reg->list_num < OR1KNUMCOREREGS) {
buf_set_u32(reg->value, 0, 32, value);
- reg->dirty = 1;
- reg->valid = 1;
+ reg->dirty = true;
+ reg->valid = true;
} else {
/* This is an spr, write it to the HW */
int retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
or1k_reg->spr_num, 1, &value);
if (retval != ERROR_OK) {
- LOG_ERROR("Error while writing spr 0x%08x", or1k_reg->spr_num);
+ LOG_ERROR("Error while writing spr 0x%08" PRIx32, or1k_reg->spr_num);
return retval;
}
}
struct or1k_common *or1k = target_to_or1k(target);
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- struct reg *reg_list = malloc((or1k->nb_regs) * sizeof(struct reg));
+ struct reg *reg_list = calloc(or1k->nb_regs, sizeof(struct reg));
struct or1k_core_reg *arch_info =
malloc((or1k->nb_regs) * sizeof(struct or1k_core_reg));
struct reg_feature *feature;
reg_list[i].group = or1k_core_reg_list_arch_info[i].group;
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
+ reg_list[i].dirty = false;
+ reg_list[i].valid = false;
reg_list[i].type = &or1k_reg_type;
reg_list[i].arch_info = &arch_info[i];
reg_list[i].number = i;
uint32_t resume_pc;
uint32_t debug_reg_list[OR1K_DEBUG_REG_NUM];
- LOG_DEBUG("Addr: 0x%x, stepping: %s, handle breakpoints %s\n",
+ LOG_DEBUG("Addr: 0x%" PRIx32 ", stepping: %s, handle breakpoints %s\n",
address, step ? "yes" : "no", handle_breakpoints ? "yes" : "no");
if (target->state != TARGET_HALTED) {
/* Single step past breakpoint at current address */
breakpoint = breakpoint_find(target, resume_pc);
if (breakpoint) {
- LOG_DEBUG("Unset breakpoint at 0x%08x", breakpoint->address);
+ LOG_DEBUG("Unset breakpoint at 0x%08" TARGET_PRIxADDR, breakpoint->address);
retval = or1k_remove_breakpoint(target, breakpoint);
if (retval != ERROR_OK)
return retval;
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
- LOG_DEBUG("Target resumed at 0x%08x", resume_pc);
+ LOG_DEBUG("Target resumed at 0x%08" PRIx32, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
- LOG_DEBUG("Target debug resumed at 0x%08x", resume_pc);
+ LOG_DEBUG("Target debug resumed at 0x%08" PRIx32, resume_pc);
}
return ERROR_OK;
}
static int or1k_resume(struct target *target, int current,
- uint32_t address, int handle_breakpoints, int debug_execution)
+ target_addr_t address, int handle_breakpoints,
+ int debug_execution)
{
return or1k_resume_or_step(target, current, address,
handle_breakpoints,
}
static int or1k_step(struct target *target, int current,
- uint32_t address, int handle_breakpoints)
+ target_addr_t address, int handle_breakpoints)
{
return or1k_resume_or_step(target, current, address,
handle_breakpoints,
struct or1k_du *du_core = or1k_to_du(or1k);
uint8_t data;
- LOG_DEBUG("Adding breakpoint: addr 0x%08x, len %d, type %d, set: %d, id: %d",
+ LOG_DEBUG("Adding breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRId32,
breakpoint->address, breakpoint->length, breakpoint->type,
breakpoint->set, breakpoint->unique_id);
1,
&data);
if (retval != ERROR_OK) {
- LOG_ERROR("Error while reading the instruction at 0x%08x",
+ LOG_ERROR("Error while reading the instruction at 0x%08" TARGET_PRIxADDR,
breakpoint->address);
return retval;
}
memcpy(breakpoint->orig_instr, &data, breakpoint->length);
/* Sub in the OR1K trap instruction */
- uint32_t or1k_trap_insn = OR1K_TRAP_INSTR;
+ uint8_t or1k_trap_insn[4];
+ target_buffer_set_u32(target, or1k_trap_insn, OR1K_TRAP_INSTR);
retval = du_core->or1k_jtag_write_memory(&or1k->jtag,
breakpoint->address,
4,
1,
- (uint8_t *)&or1k_trap_insn);
+ or1k_trap_insn);
if (retval != ERROR_OK) {
- LOG_ERROR("Error while writing OR1K_TRAP_INSTR at 0x%08x",
+ LOG_ERROR("Error while writing OR1K_TRAP_INSTR at 0x%08" TARGET_PRIxADDR,
breakpoint->address);
return retval;
}
/* invalidate instruction cache */
+ uint32_t addr = breakpoint->address;
retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
- OR1K_ICBIR_CPU_REG_ADD, 1, &breakpoint->address);
+ OR1K_ICBIR_CPU_REG_ADD, 1, &addr);
if (retval != ERROR_OK) {
LOG_ERROR("Error while invalidating the ICACHE");
return retval;
struct or1k_common *or1k = target_to_or1k(target);
struct or1k_du *du_core = or1k_to_du(or1k);
- LOG_DEBUG("Removing breakpoint: addr 0x%08x, len %d, type %d, set: %d, id: %d",
+ LOG_DEBUG("Removing breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRId32,
breakpoint->address, breakpoint->length, breakpoint->type,
breakpoint->set, breakpoint->unique_id);
breakpoint->orig_instr);
if (retval != ERROR_OK) {
- LOG_ERROR("Error while writing back the instruction at 0x%08x",
+ LOG_ERROR("Error while writing back the instruction at 0x%08" TARGET_PRIxADDR,
breakpoint->address);
return retval;
}
/* invalidate instruction cache */
+ uint32_t addr = breakpoint->address;
retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
- OR1K_ICBIR_CPU_REG_ADD, 1, &breakpoint->address);
+ OR1K_ICBIR_CPU_REG_ADD, 1, &addr);
if (retval != ERROR_OK) {
LOG_ERROR("Error while invalidating the ICACHE");
return retval;
return ERROR_OK;
}
-static int or1k_read_memory(struct target *target, uint32_t address,
+static int or1k_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct or1k_common *or1k = target_to_or1k(target);
struct or1k_du *du_core = or1k_to_du(or1k);
- LOG_DEBUG("Read memory at 0x%08x, size: %d, count: 0x%08x", address, size, count);
+ LOG_DEBUG("Read memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_UNALIGNED_ACCESS;
}
- /* or1k_read_memory with size 4/2 returns uint32_t/uint16_t in host */
- /* endianness, but byte array should represent target endianness */
-
- void *t = NULL;
- if (size > 1) {
- t = malloc(count * size * sizeof(uint8_t));
- if (t == NULL) {
- LOG_ERROR("Out of memory");
- return ERROR_FAIL;
- }
- } else
- t = buffer;
-
-
- int retval = du_core->or1k_jtag_read_memory(&or1k->jtag, address,
- size, count, t);
-
- if (retval == ERROR_OK) {
- switch (size) {
- case 4:
- target_buffer_set_u32_array(target, buffer, count, t);
- break;
- case 2:
- target_buffer_set_u16_array(target, buffer, count, t);
- break;
- }
- }
-
- if ((size > 1) && (t != NULL))
- free(t);
-
- return ERROR_OK;
+ return du_core->or1k_jtag_read_memory(&or1k->jtag, address, size, count, buffer);
}
-static int or1k_write_memory(struct target *target, uint32_t address,
+static int or1k_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct or1k_common *or1k = target_to_or1k(target);
struct or1k_du *du_core = or1k_to_du(or1k);
- LOG_DEBUG("Write memory at 0x%08x, size: %d, count: 0x%08x", address, size, count);
+ LOG_DEBUG("Write memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
if (target->state != TARGET_HALTED) {
LOG_WARNING("Target not halted");
return ERROR_TARGET_UNALIGNED_ACCESS;
}
- /* or1k_write_memory with size 4/2 requires uint32_t/uint16_t in host */
- /* endianness, but byte array represents target endianness */
-
- void *t = NULL;
- if (size > 1) {
- t = malloc(count * size * sizeof(uint8_t));
- if (t == NULL) {
- LOG_ERROR("Out of memory");
- return ERROR_FAIL;
- }
-
- switch (size) {
- case 4:
- target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
- break;
- case 2:
- target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
- break;
- }
- buffer = t;
- }
-
- int retval = du_core->or1k_jtag_write_memory(&or1k->jtag, address, size, count, buffer);
-
- if (t != NULL)
- free(t);
-
- if (retval != ERROR_OK)
- return retval;
-
- return ERROR_OK;
+ return du_core->or1k_jtag_write_memory(&or1k->jtag, address, size, count, buffer);
}
static int or1k_init_target(struct command_context *cmd_ctx,
or1k->jtag.tap = target->tap;
or1k->jtag.or1k_jtag_inited = 0;
or1k->jtag.or1k_jtag_module_selected = -1;
+ or1k->jtag.target = target;
or1k_build_reg_cache(target);
static int or1k_target_create(struct target *target, Jim_Interp *interp)
{
- struct or1k_common *or1k = calloc(1, sizeof(struct or1k_common));
-
if (target->tap == NULL)
return ERROR_FAIL;
+ struct or1k_common *or1k = calloc(1, sizeof(struct or1k_common));
+
target->arch_info = or1k;
or1k_create_reg_list(target);
or1k_tap_vjtag_register();
+ or1k_tap_xilinx_bscan_register();
or1k_tap_mohor_register();
or1k_du_adv_register();
return ERROR_FAIL;
}
-static int or1k_checksum_memory(struct target *target, uint32_t address,
+static int or1k_checksum_memory(struct target *target, target_addr_t address,
uint32_t count, uint32_t *checksum) {
return ERROR_FAIL;
}
+static int or1k_profiling(struct target *target, uint32_t *samples,
+ uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
+{
+ struct timeval timeout, now;
+ struct or1k_common *or1k = target_to_or1k(target);
+ struct or1k_du *du_core = or1k_to_du(or1k);
+ int retval = ERROR_OK;
+
+ gettimeofday(&timeout, NULL);
+ timeval_add_time(&timeout, seconds, 0);
+
+ LOG_INFO("Starting or1k profiling. Sampling npc as fast as we can...");
+
+ /* Make sure the target is running */
+ target_poll(target);
+ if (target->state == TARGET_HALTED)
+ retval = target_resume(target, 1, 0, 0, 0);
+
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Error while resuming target");
+ return retval;
+ }
+
+ uint32_t sample_count = 0;
+
+ for (;;) {
+ uint32_t reg_value;
+ retval = du_core->or1k_jtag_read_cpu(&or1k->jtag, GROUP0 + 16 /* NPC */, 1, ®_value);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Error while reading NPC");
+ return retval;
+ }
+
+ samples[sample_count++] = reg_value;
+
+ gettimeofday(&now, NULL);
+ if ((sample_count >= max_num_samples) || timeval_compare(&now, &timeout) > 0) {
+ LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
+ break;
+ }
+ }
+
+ *num_samples = sample_count;
+ return retval;
+}
+
COMMAND_HANDLER(or1k_tap_select_command_handler)
{
struct target *target = get_current_target(CMD_CTX);
or1k_add_reg(target, &new_reg);
- LOG_DEBUG("Add reg \"%s\" @ 0x%08x, group \"%s\", feature \"%s\"",
+ LOG_DEBUG("Add reg \"%s\" @ 0x%08" PRIx32 ", group \"%s\", feature \"%s\"",
new_reg.name, addr, new_reg.group, new_reg.feature);
return ERROR_OK;
static const struct command_registration or1k_hw_ip_command_handlers[] = {
{
- "tap_select",
+ .name = "tap_select",
.handler = or1k_tap_select_command_handler,
.mode = COMMAND_ANY,
.usage = "tap_select name",
.help = "Select the TAP core to use",
},
{
- "tap_list",
+ .name = "tap_list",
.handler = or1k_tap_list_command_handler,
.mode = COMMAND_ANY,
.usage = "tap_list",
.help = "Display available TAP core",
},
{
- "du_select",
+ .name = "du_select",
.handler = or1k_du_select_command_handler,
.mode = COMMAND_ANY,
.usage = "du_select name",
.help = "Select the Debug Unit core to use",
},
{
- "du_list",
+ .name = "du_list",
.handler = or1k_du_list_command_handler,
.mode = COMMAND_ANY,
.usage = "select_tap name",
static const struct command_registration or1k_reg_command_handlers[] = {
{
- "addreg",
+ .name = "addreg",
.handler = or1k_addreg_command_handler,
.mode = COMMAND_ANY,
.usage = "addreg name addr feature group",
.examine = or1k_examine,
.get_gdb_fileio_info = or1k_get_gdb_fileio_info,
+
+ .profiling = or1k_profiling,
};
Code Review / openocd.git / blobdiff