reg_value = or1k->core_regs[num];
buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value);
- or1k->core_cache->reg_list[num].valid = 1;
- or1k->core_cache->reg_list[num].dirty = 0;
+ or1k->core_cache->reg_list[num].valid = true;
+ or1k->core_cache->reg_list[num].dirty = false;
} else {
/* This is an spr, always read value from HW */
int retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
or1k->core_regs[num] = reg_value;
LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value);
- or1k->core_cache->reg_list[num].valid = 1;
- or1k->core_cache->reg_list[num].dirty = 0;
+ or1k->core_cache->reg_list[num].valid = true;
+ or1k->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
if (or1k_reg->list_num < OR1KNUMCOREREGS) {
buf_set_u32(reg->value, 0, 32, value);
- reg->dirty = 1;
- reg->valid = 1;
+ reg->dirty = true;
+ reg->valid = true;
} else {
/* This is an spr, write it to the HW */
int retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
reg_list[i].group = or1k_core_reg_list_arch_info[i].group;
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
+ reg_list[i].dirty = false;
+ reg_list[i].valid = false;
reg_list[i].type = &or1k_reg_type;
reg_list[i].arch_info = &arch_info[i];
reg_list[i].number = i;
samples[sample_count++] = reg_value;
gettimeofday(&now, NULL);
- if ((sample_count >= max_num_samples) ||
- ((now.tv_sec >= timeout.tv_sec) && (now.tv_usec >= timeout.tv_usec))) {
+ if ((sample_count >= max_num_samples) || timeval_compare(&now, &timeout) > 0) {
LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
break;
}