riscv: Regenerated debug_defines.h and encoding.h

[openocd.git] / src / target / riscv / debug_defines.h

diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h
index b5104d53060f58186053c2430c0ee9c643e29724..5c9eef4eafee2877ed18c8e5d0da9f3554fb5106 100644 (file)
--- a/src/target/riscv/debug_defines.h
+++ b/src/target/riscv/debug_defines.h
@@ -1,6 +1,6 @@
 /*
  * This file is auto-generated by running 'make debug_defines.h' in
- * https://github.com/riscv/riscv-debug-spec/ (63c985f)
+ * https://github.com/riscv/riscv-debug-spec/ (3dfe4f7)
  * License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0)
  */
 
@@ -266,7 +266,7 @@
  *
  * 1: An {\tt ebreak} instruction was executed. (priority 3)
  *
- * 2: The Trigger Module caused a breakpoint exception. (priority 4)
+ * 2: A Trigger Module trigger fired with action=0. (priority 4)
  *
  * 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
  * (priority 1)
@@ -461,7 +461,7 @@
  *
  * \FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem
  * regarding triggers with action=0 firing in M-mode trap handlers. See
- * Section~\ref{sec:mmtrigger} for more details.
+ * Section~\ref{sec:nativetrigger} for more details.
  *
  * When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
  * \FcsrTcontrolMte.
@@ -811,8 +811,9 @@
 #define CSR_MCONTROL6_VU_LENGTH             1
 #define CSR_MCONTROL6_VU                    (0x1ULL << CSR_MCONTROL6_VU_OFFSET)
 /*
- * If this bit is implemented, the hardware sets it when this
- * trigger matches. The trigger's user can set or clear it at any
+ * If this bit is implemented then it must become set when this
+ * trigger fires and may become set when this trigger matches.
+ * The trigger's user can set or clear it at any
  * time. It is used to determine which
  * trigger(s) matched.  If the bit is not implemented, it is always 0
  * and writing it has no effect.
@@ -1237,7 +1238,8 @@
 #define CSR_ETRIGGER_VU                     (0x1ULL << CSR_ETRIGGER_VU_OFFSET)
 /*
  * When set, non-maskable interrupts cause this
- * trigger to fire, regardless of the values of \FcsrEtriggerM, \FcsrEtriggerS, and \FcsrEtriggerU.
+ * trigger to fire, regardless of the values of \FcsrEtriggerM,
+ * \FcsrEtriggerS, \FcsrEtriggerU, \FcsrEtriggerVs, and \FcsrEtriggerVu.
  */
 #define CSR_ETRIGGER_NMI_OFFSET             10
 #define CSR_ETRIGGER_NMI_LENGTH             1
@@ -1361,10 +1363,15 @@
  * 1: This trigger will only match if the low bits of
  * \RcsrScontext equal \FcsrTextraThirtytwoSvalue.
  *
- * 2: This trigger will only match if the currently active ASID
- * value, from either \Rsatp or \Rvsatp,
- * equals the lower ASIDMAX (defined in the Privileged Spec) bits of
+ * 2: This trigger will only match if:
+ * \begin{itemize}[noitemsep,nolistsep]
+ * \item the mode is VS-mode or VU-mode and ASID in \Rvsatp
+ * equals the lower ASIDMAX (defined in the Privileged Spec) bits
+ * of \FcsrTextraThirtytwoSvalue.
+ * \item in all other modes, ASID in \Rsatp equals the lower
+ * ASIDMAX (defined in the Privileged Spec) bits of
  * \FcsrTextraThirtytwoSvalue.
+ * \end{itemize}
  *
  * This field should be tied to 0 when S-mode is not supported.
  */