/*
* This file is auto-generated by running 'make debug_defines.h' in
- * https://github.com/riscv/riscv-debug-spec/ (30b1a97)
+ * https://github.com/riscv/riscv-debug-spec/ (63c985f)
+ * License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0)
*/
#define DTM_IDCODE 0x01
/*
* 0: Version described in spec version 0.11.
*
- * 1: Version described in spec version 0.13.
+ * 1: Version described in spec versions 0.13 and 1.0.
*
* 15: Version not described in any available version of this spec.
*/
#define DTM_DMI_OP (0x3ULL << DTM_DMI_OP_OFFSET)
#define CSR_DCSR 0x7b0
/*
- * 0: There is no external debug support.
+ * 0: There is no debug support.
*
- * 4: External debug support exists as it is described in this document.
+ * 4: Debug support exists as it is described in this document.
*
- * 15: There is external debug support, but it does not conform to any
+ * 15: There is debug support, but it does not conform to any
* available version of this spec.
*/
-#define CSR_DCSR_XDEBUGVER_OFFSET 28
-#define CSR_DCSR_XDEBUGVER_LENGTH 4
-#define CSR_DCSR_XDEBUGVER (0xfU << CSR_DCSR_XDEBUGVER_OFFSET)
+#define CSR_DCSR_DEBUGVER_OFFSET 28
+#define CSR_DCSR_DEBUGVER_LENGTH 4
+#define CSR_DCSR_DEBUGVER (0xfU << CSR_DCSR_DEBUGVER_OFFSET)
+/*
+ * 0: {\tt ebreak} instructions in VS-mode behave as described in the
+ * Privileged Spec.
+ *
+ * 1: {\tt ebreak} instructions in VS-mode enter Debug Mode.
+ *
+ * This bit is hardwired to 0 if the hart does not support virtualization mode.
+ */
+#define CSR_DCSR_EBREAKVS_OFFSET 17
+#define CSR_DCSR_EBREAKVS_LENGTH 1
+#define CSR_DCSR_EBREAKVS (0x1U << CSR_DCSR_EBREAKVS_OFFSET)
+/*
+ * 0: {\tt ebreak} instructions in VU-mode behave as described in the
+ * Privileged Spec.
+ *
+ * 1: {\tt ebreak} instructions in VU-mode enter Debug Mode.
+ *
+ * This bit is hardwired to 0 if the hart does not support virtualization mode.
+ */
+#define CSR_DCSR_EBREAKVU_OFFSET 16
+#define CSR_DCSR_EBREAKVU_LENGTH 1
+#define CSR_DCSR_EBREAKVU (0x1U << CSR_DCSR_EBREAKVU_OFFSET)
/*
* 0: {\tt ebreak} instructions in M-mode behave as described in the
* Privileged Spec.
*
* 1: {\tt ebreak} instructions in S-mode enter Debug Mode.
*
- * This bit is hardwired to 0 if the hart does not support S mode.
+ * This bit is hardwired to 0 if the hart does not support S-mode.
*/
#define CSR_DCSR_EBREAKS_OFFSET 13
#define CSR_DCSR_EBREAKS_LENGTH 1
*
* 1: {\tt ebreak} instructions in U-mode enter Debug Mode.
*
- * This bit is hardwired to 0 if the hart does not support U mode.
+ * This bit is hardwired to 0 if the hart does not support U-mode.
*/
#define CSR_DCSR_EBREAKU_OFFSET 12
#define CSR_DCSR_EBREAKU_LENGTH 1
#define CSR_DCSR_CAUSE_LENGTH 3
#define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET)
/*
- * 0: \FcsrMcontrolMprv in \Rmstatus is ignored in Debug Mode.
+ * Extends the prv field with the virtualization mode the hart was operating
+ * in when Debug Mode was entered. The encoding is described in Table
+ * \ref{tab:privlevel}.
+ * A debugger can change this value to change the hart's virtualization mode
+ * when exiting Debug Mode.
+ * This bit is hardwired to 0 on harts that do not support virtualization mode.
+ */
+#define CSR_DCSR_V_OFFSET 5
+#define CSR_DCSR_V_LENGTH 1
+#define CSR_DCSR_V (0x1U << CSR_DCSR_V_OFFSET)
+/*
+ * 0: \FcsrMstatusMprv in \Rmstatus is ignored in Debug Mode.
*
- * 1: \FcsrMcontrolMprv in \Rmstatus takes effect in Debug Mode.
+ * 1: \FcsrMstatusMprv in \Rmstatus takes effect in Debug Mode.
*
* Implementing this bit is optional. It may be tied to either 0 or 1.
*/
* 5: The trigger is an exception trigger. The remaining bits
* in this register act as described in \RcsrEtrigger.
*
+ * 6: The trigger is an address/data match trigger. The remaining bits
+ * in this register act as described in \RcsrMcontrolSix. This is similar
+ * to a type 2 trigger, but provides additional functionality and
+ * should be used instead of type 2 in newer implementations.
+ *
+ * 7: The trigger is a trigger source external to the TM. The
+ * remaining bits in this register act as described in \RcsrTmexttrigger.
+ *
* 12--14: These trigger types are available for non-standard use.
*
* 15: This trigger exists (so enumeration shouldn't terminate), but
* selected \RcsrTselect. Writes from other modes are ignored.
*
* This bit is only writable from Debug Mode.
- * When clearing this bit, the debugger should also clear the action field
+ * In ordinary use, external debuggers will always set this bit when
+ * configuring a trigger.
+ * When clearing this bit, debuggers should also clear the action field
* (whose location depends on \FcsrTdataOneType).
*/
#define CSR_TDATA1_DMODE_OFFSET (XLEN-5)
#define CSR_TINFO_INFO_LENGTH 16
#define CSR_TINFO_INFO (0xffffULL << CSR_TINFO_INFO_OFFSET)
#define CSR_TCONTROL 0x7a5
+/*
+ * \RcsrHcontext enable.
+ *
+ * 0: \RcsrHcontext is set to 0 and writes are ignored.
+ *
+ * 1: \RcsrHcontext may be written and read.
+ */
+#define CSR_TCONTROL_HCXE_OFFSET 9
+#define CSR_TCONTROL_HCXE_LENGTH 1
+#define CSR_TCONTROL_HCXE (0x1ULL << CSR_TCONTROL_HCXE_OFFSET)
+/*
+ * \RcsrScontext enable.
+ *
+ * 0: \RcsrScontext is set to 0 and writes are ignored.
+ *
+ * 1: \RcsrScontext may be written and read.
+ *
+ * Enabling \RcsrScontext can be a security risk in a
+ * virtualized system with a hypervisor that does not swap \RcsrScontext.
+ */
+#define CSR_TCONTROL_SCXE_OFFSET 8
+#define CSR_TCONTROL_SCXE_LENGTH 1
+#define CSR_TCONTROL_SCXE (0x1ULL << CSR_TCONTROL_SCXE_OFFSET)
/*
* M-mode previous trigger enable field.
*
+ * \FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem
+ * regarding triggers with action=0 firing in M-mode trap handlers. See
+ * Section~\ref{sec:mmtrigger} for more details.
+ *
* When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
* \FcsrTcontrolMte.
*/
#define CSR_TCONTROL_MTE_OFFSET 3
#define CSR_TCONTROL_MTE_LENGTH 1
#define CSR_TCONTROL_MTE (0x1ULL << CSR_TCONTROL_MTE_OFFSET)
-#define CSR_MCONTEXT 0x7a8
+#define CSR_HCONTEXT 0x6a8
/*
- * Machine mode software can write a context number to this register,
+ * Hypervisor mode software can write a context number to this register,
* which can be used to set triggers that only fire in that specific
* context.
*
* An implementation may tie any number of upper bits in this field to
- * 0. It's recommended to implement no more than 6 bits on RV32, and
- * 13 on RV64.
+ * 0. If the H extension is not implemented, it's recommended to implement
+ * no more than 6 bits on RV32 and 13 on RV64 (as visible through the
+ * \RcsrMcontext register). If the H extension is implemented,
+ * it's recommended to implement no more than 7 bits on RV32
+ * and 14 on RV64.
*/
-#define CSR_MCONTEXT_MCONTEXT_OFFSET 0
-#define CSR_MCONTEXT_MCONTEXT_LENGTH XLEN
-#define CSR_MCONTEXT_MCONTEXT (((1L << XLEN) - 1) << CSR_MCONTEXT_MCONTEXT_OFFSET)
-#define CSR_SCONTEXT 0x7aa
+#define CSR_HCONTEXT_HCONTEXT_OFFSET 0
+#define CSR_HCONTEXT_HCONTEXT_LENGTH XLEN
+#define CSR_HCONTEXT_HCONTEXT (((1L << XLEN) - 1) << CSR_HCONTEXT_HCONTEXT_OFFSET)
+#define CSR_SCONTEXT 0x5a8
/*
* Supervisor mode software can write a context number to this
* register, which can be used to set triggers that only fire in that
#define CSR_SCONTEXT_DATA_OFFSET 0
#define CSR_SCONTEXT_DATA_LENGTH XLEN
#define CSR_SCONTEXT_DATA (((1L << XLEN) - 1) << CSR_SCONTEXT_DATA_OFFSET)
+#define CSR_MCONTEXT 0x7a8
+#define CSR_MSCONTEXT 0x7aa
#define CSR_MCONTROL 0x7a1
#define CSR_MCONTROL_TYPE_OFFSET (XLEN-4)
#define CSR_MCONTROL_TYPE_LENGTH 4
/*
* Specifies the largest naturally aligned powers-of-two (NAPOT) range
* supported by the hardware when \FcsrMcontrolMatch is 1. The value is the
- * logarithm base 2 of the
- * number of bytes in that range. A value of 0 indicates that only
- * exact value matches are supported (one byte range). A value of 63
- * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in
- * size.
+ * logarithm base 2 of the number of bytes in that range.
+ * A value of 0 indicates \FcsrMcontrolMatch 1 is not supported.
+ * A value of 63 corresponds to the maximum NAPOT range, which is
+ * $2^{63}$ bytes in size.
*/
#define CSR_MCONTROL_MASKMAX_OFFSET (XLEN-11)
#define CSR_MCONTROL_MASKMAX_LENGTH 6
#define CSR_MCONTROL_SIZEHI_LENGTH 2
#define CSR_MCONTROL_SIZEHI (0x3ULL << CSR_MCONTROL_SIZEHI_OFFSET)
/*
- * If this bit is implemented, the hardware sets it when this
- * trigger matches. The trigger's user can set or clear it at any
+ * If this bit is implemented then it must become set when this
+ * trigger fires and may become set when this trigger matches.
+ * The trigger's user can set or clear it at any
* time. It is used to determine which
* trigger(s) matched. If the bit is not implemented, it is always 0
* and writing it has no effect.
#define CSR_MCONTROL_HIT_LENGTH 1
#define CSR_MCONTROL_HIT (0x1ULL << CSR_MCONTROL_HIT_OFFSET)
/*
- * 0: Perform a match on the lowest virtual address of the access. In
- * addition, it is recommended that the trigger also fires if any of
- * the other accessed virtual addresses match.
+ * This bit determines the contents of the XLEN-bit compare values.
+ *
+ * 0: There is at least one compare value and it contains the lowest
+ * virtual address of the access.
+ * It is recommended that there are additional compare values for
+ * the other accessed virtual addresses.
* (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
* and the other addresses are 0x4001, 0x4002, and 0x4003.)
*
- * 1: Perform a match on the data value loaded or stored, or the
- * instruction executed.
+ * 1: There is exactly one compare value and it contains the data
+ * value loaded or stored, or the instruction executed.
+ * Any bits beyond the size of the data access will contain 0.
*/
#define CSR_MCONTROL_SELECT_OFFSET 19
#define CSR_MCONTROL_SELECT_LENGTH 1
#define CSR_MCONTROL_SELECT (0x1ULL << CSR_MCONTROL_SELECT_OFFSET)
/*
* 0: The action for this trigger will be taken just before the
- * instruction that triggered it is executed, but after all preceding
- * instructions are committed. \Rmepc or \RcsrDpc (depending on
- * \FcsrMcontrolAction) must be set to the virtual address of the
+ * instruction that triggered it is committed, but after all preceding
+ * instructions are committed. \Rxepc or \RcsrDpc (depending
+ * on \FcsrMcontrolAction) must be set to the virtual address of the
* instruction that matched.
*
- * If this is combined with \FcsrMcontrolLoad then a memory access will be
+ * If this is combined with \FcsrMcontrolLoad and
+ * \FcsrMcontrolSelect=1 then a memory access will be
* performed (including any side effects of performing such an access) even
* though the load will not update its destination register. Debuggers
* should consider this when setting such breakpoints on, for example,
* memory-mapped I/O addresses.
*
* 1: The action for this trigger will be taken after the instruction
- * that triggered it is executed. It should be taken before the next
- * instruction is executed, but it is better to implement triggers imprecisely
- * than to not implement them at all.
- * \Rmepc or \RcsrDpc (depending on \FcsrMcontrolAction) must be set to
+ * that triggered it is committed. It should be taken before the next
+ * instruction is committed, but it is better to implement triggers imprecisely
+ * than to not implement them at all. \Rxepc or
+ * \RcsrDpc (depending on \FcsrMcontrolAction) must be set to
* the virtual address of the next instruction that must be executed to
* preserve the program flow.
*
* execution of 128-bit instructions.
*
* An implementation must support the value of 0, but all other values
- * are optional. It is recommended to support triggers for every
- * access size the hart supports, as well as for every instruction
- * size the hart supports.
+ * are optional. When an implementation supports address triggers
+ * (\FcsrMcontrolSelect=0), it is recommended that those triggers
+ * support every access size that the hart supports, as well as for
+ * every instruction size that the hart supports.
+ *
+ * Implementations such as RV32D or RV64V are able to perform loads
+ * and stores that are wider than XLEN. Custom extensions may also
+ * support instructions that are wider than XLEN. Because
+ * \RcsrTdataTwo is of size XLEN, there is a known limitation that
+ * data value triggers (\FcsrMcontrolSelect=1) can only be supported
+ * for access sizes up to XLEN bits. When an implementation supports
+ * data value triggers (\FcsrMcontrolSelect=1), it is recommended
+ * that those triggers support every access size up to XLEN that the
+ * hart supports, as well as for every instruction length up to XLEN
+ * that the hart supports.
*/
#define CSR_MCONTROL_SIZELO_OFFSET 16
#define CSR_MCONTROL_SIZELO_LENGTH 2
* trigger will be taken if and only if all the triggers in the chain
* match at the same time.
*
+ * Debuggers should not terminate a chain with a trigger with a
+ * different type. It is undefined when exactly such a chain fires.
+ *
* Because \FcsrMcontrolChain affects the next trigger, hardware must zero it in
* writes to \RcsrMcontrol that set \FcsrTdataOneDmode to 0 if the next trigger has
* \FcsrTdataOneDmode of 1.
#define CSR_MCONTROL_CHAIN_LENGTH 1
#define CSR_MCONTROL_CHAIN (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET)
/*
- * 0: Matches when the value equals \RcsrTdataTwo.
+ * 0: Matches when any compare value equals \RcsrTdataTwo.
*
- * 1: Matches when the top M bits of the value match the top M bits of
- * \RcsrTdataTwo. M is XLEN-1 minus the index of the least-significant
+ * 1: Matches when the top $M$ bits of any compare value match the top
+ * $M$ bits of \RcsrTdataTwo.
+ * $M$ is $|XLEN|-1$ minus the index of the least-significant
* bit containing 0 in \RcsrTdataTwo. Debuggers should only write values
- * to \RcsrTdataTwo such that M + \FcsrMcontrolMaskmax $\geq$ XLEN, otherwise it's
- * undefined on what conditions the trigger will fire.
+ * to \RcsrTdataTwo such that $M + $\FcsrMcontrolMaskmax$ \geq |XLEN|$
+ * and $M\gt0$ , otherwise it's undefined on what conditions the
+ * trigger will match.
*
- * 2: Matches when the value is greater than (unsigned) or equal to
- * \RcsrTdataTwo.
+ * 2: Matches when any compare value is greater than (unsigned) or
+ * equal to \RcsrTdataTwo.
*
- * 3: Matches when the value is less than (unsigned) \RcsrTdataTwo.
+ * 3: Matches when any compare value is less than (unsigned)
+ * \RcsrTdataTwo.
*
- * 4: Matches when the lower half of the value equals the lower half
- * of \RcsrTdataTwo after the lower half of the value is ANDed with the
- * upper half of \RcsrTdataTwo.
+ * 4: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
+ * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
+ * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with
+ * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
*
- * 5: Matches when the upper half of the value equals the lower half
- * of \RcsrTdataTwo after the upper half of the value is ANDed with the
- * upper half of \RcsrTdataTwo.
+ * 5: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare
+ * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
+ * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with
+ * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
*
* 8: Matches when \FcsrMcontrolMatch$=0$ would not match.
*
* 13: Matches when \FcsrMcontrolMatch$=5$ would not match.
*
* Other values are reserved for future use.
+ *
+ * All comparisons only look at the lower XLEN (in the current mode)
+ * bits of the compare values and of \RcsrTdataTwo.
+ * When \FcsrMcontrolSelect=1 and access size is N, this is further
+ * reduced, and comparisons only look at the lower N bits of the
+ * compare values and of \RcsrTdataTwo.
*/
#define CSR_MCONTROL_MATCH_OFFSET 7
#define CSR_MCONTROL_MATCH_LENGTH 4
#define CSR_MCONTROL_M_LENGTH 1
#define CSR_MCONTROL_M (0x1ULL << CSR_MCONTROL_M_OFFSET)
/*
- * When set, enable this trigger in S-mode.
+ * When set, enable this trigger in S/HS-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * S-mode.
*/
#define CSR_MCONTROL_S_OFFSET 4
#define CSR_MCONTROL_S_LENGTH 1
#define CSR_MCONTROL_S (0x1ULL << CSR_MCONTROL_S_OFFSET)
/*
* When set, enable this trigger in U-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * U-mode.
*/
#define CSR_MCONTROL_U_OFFSET 3
#define CSR_MCONTROL_U_LENGTH 1
#define CSR_MCONTROL_LOAD_OFFSET 0
#define CSR_MCONTROL_LOAD_LENGTH 1
#define CSR_MCONTROL_LOAD (0x1ULL << CSR_MCONTROL_LOAD_OFFSET)
+#define CSR_MCONTROL6 0x7a1
+#define CSR_MCONTROL6_TYPE_OFFSET (XLEN-4)
+#define CSR_MCONTROL6_TYPE_LENGTH 4
+#define CSR_MCONTROL6_TYPE (0xfULL << CSR_MCONTROL6_TYPE_OFFSET)
+#define CSR_MCONTROL6_DMODE_OFFSET (XLEN-5)
+#define CSR_MCONTROL6_DMODE_LENGTH 1
+#define CSR_MCONTROL6_DMODE (0x1ULL << CSR_MCONTROL6_DMODE_OFFSET)
+/*
+ * When set, enable this trigger in VS-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * virtualization mode.
+ */
+#define CSR_MCONTROL6_VS_OFFSET 24
+#define CSR_MCONTROL6_VS_LENGTH 1
+#define CSR_MCONTROL6_VS (0x1ULL << CSR_MCONTROL6_VS_OFFSET)
+/*
+ * When set, enable this trigger in VU-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * virtualization mode.
+ */
+#define CSR_MCONTROL6_VU_OFFSET 23
+#define CSR_MCONTROL6_VU_LENGTH 1
+#define CSR_MCONTROL6_VU (0x1ULL << CSR_MCONTROL6_VU_OFFSET)
+/*
+ * If this bit is implemented, the hardware sets it when this
+ * trigger matches. The trigger's user can set or clear it at any
+ * time. It is used to determine which
+ * trigger(s) matched. If the bit is not implemented, it is always 0
+ * and writing it has no effect.
+ */
+#define CSR_MCONTROL6_HIT_OFFSET 22
+#define CSR_MCONTROL6_HIT_LENGTH 1
+#define CSR_MCONTROL6_HIT (0x1ULL << CSR_MCONTROL6_HIT_OFFSET)
+/*
+ * This bit determines the contents of the XLEN-bit compare values.
+ *
+ * 0: There is at least one compare value and it contains the lowest
+ * virtual address of the access.
+ * In addition, it is recommended that there are additional compare
+ * values for the other accessed virtual addresses match.
+ * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
+ * and the other addresses are 0x4001, 0x4002, and 0x4003.)
+ *
+ * 1: There is exactly one compare value and it contains the data
+ * value loaded or stored, or the instruction executed.
+ * Any bits beyond the size of the data access will contain 0.
+ */
+#define CSR_MCONTROL6_SELECT_OFFSET 21
+#define CSR_MCONTROL6_SELECT_LENGTH 1
+#define CSR_MCONTROL6_SELECT (0x1ULL << CSR_MCONTROL6_SELECT_OFFSET)
+/*
+ * 0: The action for this trigger will be taken just before the
+ * instruction that triggered it is committed, but after all preceding
+ * instructions are committed. \Rxepc or \RcsrDpc (depending
+ * on \FcsrMcontrolSixAction) must be set to the virtual address of the
+ * instruction that matched.
+ *
+ * If this is combined with \FcsrMcontrolSixLoad and
+ * \FcsrMcontrolSixSelect=1 then a memory access will be
+ * performed (including any side effects of performing such an access) even
+ * though the load will not update its destination register. Debuggers
+ * should consider this when setting such breakpoints on, for example,
+ * memory-mapped I/O addresses.
+ *
+ * 1: The action for this trigger will be taken after the instruction
+ * that triggered it is committed. It should be taken before the next
+ * instruction is committed, but it is better to implement triggers imprecisely
+ * than to not implement them at all. \Rxepc or
+ * \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to
+ * the virtual address of the next instruction that must be executed to
+ * preserve the program flow.
+ *
+ * Most hardware will only implement one timing or the other, possibly
+ * dependent on \FcsrMcontrolSixSelect, \FcsrMcontrolSixExecute,
+ * \FcsrMcontrolSixLoad, and \FcsrMcontrolSixStore. This bit
+ * primarily exists for the hardware to communicate to the debugger
+ * what will happen. Hardware may implement the bit fully writable, in
+ * which case the debugger has a little more control.
+ *
+ * Data load triggers with \FcsrMcontrolSixTiming of 0 will result in the same load
+ * happening again when the debugger lets the hart run. For data load
+ * triggers, debuggers must first attempt to set the breakpoint with
+ * \FcsrMcontrolSixTiming of 1.
+ *
+ * If a trigger with \FcsrMcontrolSixTiming of 0 matches, it is
+ * implementation-dependent whether that prevents a trigger with
+ * \FcsrMcontrolSixTiming of 1 matching as well.
+ */
+#define CSR_MCONTROL6_TIMING_OFFSET 20
+#define CSR_MCONTROL6_TIMING_LENGTH 1
+#define CSR_MCONTROL6_TIMING (0x1ULL << CSR_MCONTROL6_TIMING_OFFSET)
+/*
+ * 0: The trigger will attempt to match against an access of any size.
+ * The behavior is only well-defined if $|select|=0$, or if the access
+ * size is XLEN.
+ *
+ * 1: The trigger will only match against 8-bit memory accesses.
+ *
+ * 2: The trigger will only match against 16-bit memory accesses or
+ * execution of 16-bit instructions.
+ *
+ * 3: The trigger will only match against 32-bit memory accesses or
+ * execution of 32-bit instructions.
+ *
+ * 4: The trigger will only match against execution of 48-bit instructions.
+ *
+ * 5: The trigger will only match against 64-bit memory accesses or
+ * execution of 64-bit instructions.
+ *
+ * 6: The trigger will only match against execution of 80-bit instructions.
+ *
+ * 7: The trigger will only match against execution of 96-bit instructions.
+ *
+ * 8: The trigger will only match against execution of 112-bit instructions.
+ *
+ * 9: The trigger will only match against 128-bit memory accesses or
+ * execution of 128-bit instructions.
+ *
+ * An implementation must support the value of 0, but all other values
+ * are optional. When an implementation supports address triggers
+ * (\FcsrMcontrolSixSelect=0), it is recommended that those triggers
+ * support every access size that the hart supports, as well as for
+ * every instruction size that the hart supports.
+ *
+ * Implementations such as RV32D or RV64V are able to perform loads
+ * and stores that are wider than XLEN. Custom extensions may also
+ * support instructions that are wider than XLEN. Because
+ * \RcsrTdataTwo is of size XLEN, there is a known limitation that
+ * data value triggers (\FcsrMcontrolSixSelect=1) can only be supported
+ * for access sizes up to XLEN bits. When an implementation supports
+ * data value triggers (\FcsrMcontrolSixSelect=1), it is recommended
+ * that those triggers support every access size up to XLEN that the
+ * hart supports, as well as for every instruction length up to XLEN
+ * that the hart supports.
+ */
+#define CSR_MCONTROL6_SIZE_OFFSET 16
+#define CSR_MCONTROL6_SIZE_LENGTH 4
+#define CSR_MCONTROL6_SIZE (0xfULL << CSR_MCONTROL6_SIZE_OFFSET)
+/*
+ * The action to take when the trigger fires. The values are explained
+ * in Table~\ref{tab:action}.
+ */
+#define CSR_MCONTROL6_ACTION_OFFSET 12
+#define CSR_MCONTROL6_ACTION_LENGTH 4
+#define CSR_MCONTROL6_ACTION (0xfULL << CSR_MCONTROL6_ACTION_OFFSET)
+/*
+ * 0: When this trigger matches, the configured action is taken.
+ *
+ * 1: While this trigger does not match, it prevents the trigger with
+ * the next index from matching.
+ *
+ * A trigger chain starts on the first trigger with $|chain|=1$ after
+ * a trigger with $|chain|=0$, or simply on the first trigger if that
+ * has $|chain|=1$. It ends on the first trigger after that which has
+ * $|chain|=0$. This final trigger is part of the chain. The action
+ * on all but the final trigger is ignored. The action on that final
+ * trigger will be taken if and only if all the triggers in the chain
+ * match at the same time.
+ *
+ * Debuggers should not terminate a chain with a trigger with a
+ * different type. It is undefined when exactly such a chain fires.
+ *
+ * Because \FcsrMcontrolSixChain affects the next trigger, hardware must zero it in
+ * writes to \RcsrMcontrolSix that set \FcsrTdataOneDmode to 0 if the next trigger has
+ * \FcsrTdataOneDmode of 1.
+ * In addition hardware should ignore writes to \RcsrMcontrolSix that set
+ * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and
+ * \FcsrMcontrolSixChain of 1. Debuggers must avoid the latter case by checking
+ * \FcsrMcontrolSixChain on the previous trigger if they're writing \RcsrMcontrolSix.
+ *
+ * Implementations that wish to limit the maximum length of a trigger
+ * chain (eg. to meet timing requirements) may do so by zeroing
+ * \FcsrMcontrolSixChain in writes to \RcsrMcontrolSix that would make the chain too long.
+ */
+#define CSR_MCONTROL6_CHAIN_OFFSET 11
+#define CSR_MCONTROL6_CHAIN_LENGTH 1
+#define CSR_MCONTROL6_CHAIN (0x1ULL << CSR_MCONTROL6_CHAIN_OFFSET)
+/*
+ * 0: Matches when any compare value equals \RcsrTdataTwo.
+ *
+ * 1: Matches when the top $M$ bits of any compare value match the top
+ * $M$ bits of \RcsrTdataTwo.
+ * $M$ is $|XLEN|-1$ minus the index of the least-significant bit
+ * containing 0 in \RcsrTdataTwo.
+ * \RcsrTdataTwo is WARL and bit $|maskmax6|-1$ will be set to 0 if no
+ * less significant bits are written with 0.
+ * Legal values for \RcsrTdataTwo require $M + |maskmax6| \geq |XLEN|$ and $M\gt0$.
+ * See above for how to determine maskmax6.
+ *
+ * 2: Matches when any compare value is greater than (unsigned) or
+ * equal to \RcsrTdataTwo.
+ *
+ * 3: Matches when any compare value is less than (unsigned)
+ * \RcsrTdataTwo.
+ *
+ * 4: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
+ * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
+ * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with
+ * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
+ *
+ * 5: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare
+ * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
+ * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with
+ * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
+ *
+ * 8: Matches when \FcsrMcontrolSixMatch$=0$ would not match.
+ *
+ * 9: Matches when \FcsrMcontrolSixMatch$=1$ would not match.
+ *
+ * 12: Matches when \FcsrMcontrolSixMatch$=4$ would not match.
+ *
+ * 13: Matches when \FcsrMcontrolSixMatch$=5$ would not match.
+ *
+ * Other values are reserved for future use.
+ *
+ * All comparisons only look at the lower XLEN (in the current mode)
+ * bits of the compare values and of \RcsrTdataTwo.
+ * When \FcsrMcontrolSelect=1 and access size is N, this is further
+ * reduced, and comparisons only look at the lower N bits of the
+ * compare values and of \RcsrTdataTwo.
+ */
+#define CSR_MCONTROL6_MATCH_OFFSET 7
+#define CSR_MCONTROL6_MATCH_LENGTH 4
+#define CSR_MCONTROL6_MATCH (0xfULL << CSR_MCONTROL6_MATCH_OFFSET)
+/*
+ * When set, enable this trigger in M-mode.
+ */
+#define CSR_MCONTROL6_M_OFFSET 6
+#define CSR_MCONTROL6_M_LENGTH 1
+#define CSR_MCONTROL6_M (0x1ULL << CSR_MCONTROL6_M_OFFSET)
+/*
+ * When set, enable this trigger in S/HS-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * S-mode.
+ */
+#define CSR_MCONTROL6_S_OFFSET 4
+#define CSR_MCONTROL6_S_LENGTH 1
+#define CSR_MCONTROL6_S (0x1ULL << CSR_MCONTROL6_S_OFFSET)
+/*
+ * When set, enable this trigger in U-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * U-mode.
+ */
+#define CSR_MCONTROL6_U_OFFSET 3
+#define CSR_MCONTROL6_U_LENGTH 1
+#define CSR_MCONTROL6_U (0x1ULL << CSR_MCONTROL6_U_OFFSET)
+/*
+ * When set, the trigger fires on the virtual address or opcode of an
+ * instruction that is executed.
+ */
+#define CSR_MCONTROL6_EXECUTE_OFFSET 2
+#define CSR_MCONTROL6_EXECUTE_LENGTH 1
+#define CSR_MCONTROL6_EXECUTE (0x1ULL << CSR_MCONTROL6_EXECUTE_OFFSET)
+/*
+ * When set, the trigger fires on the virtual address or data of any
+ * store.
+ */
+#define CSR_MCONTROL6_STORE_OFFSET 1
+#define CSR_MCONTROL6_STORE_LENGTH 1
+#define CSR_MCONTROL6_STORE (0x1ULL << CSR_MCONTROL6_STORE_OFFSET)
+/*
+ * When set, the trigger fires on the virtual address or data of any
+ * load.
+ */
+#define CSR_MCONTROL6_LOAD_OFFSET 0
+#define CSR_MCONTROL6_LOAD_LENGTH 1
+#define CSR_MCONTROL6_LOAD (0x1ULL << CSR_MCONTROL6_LOAD_OFFSET)
#define CSR_ICOUNT 0x7a1
#define CSR_ICOUNT_TYPE_OFFSET (XLEN-4)
#define CSR_ICOUNT_TYPE_LENGTH 4
#define CSR_ICOUNT_DMODE_OFFSET (XLEN-5)
#define CSR_ICOUNT_DMODE_LENGTH 1
#define CSR_ICOUNT_DMODE (0x1ULL << CSR_ICOUNT_DMODE_OFFSET)
+/*
+ * When set, enable this trigger in VS-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * virtualization mode.
+ */
+#define CSR_ICOUNT_VS_OFFSET 26
+#define CSR_ICOUNT_VS_LENGTH 1
+#define CSR_ICOUNT_VS (0x1ULL << CSR_ICOUNT_VS_OFFSET)
+/*
+ * When set, enable this trigger in VU-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * virtualization mode.
+ */
+#define CSR_ICOUNT_VU_OFFSET 25
+#define CSR_ICOUNT_VU_LENGTH 1
+#define CSR_ICOUNT_VU (0x1ULL << CSR_ICOUNT_VU_OFFSET)
/*
* If this bit is implemented, the hardware sets it when this
* trigger matches. The trigger's user can set or clear it at any
/*
* When count is decremented to 0, the trigger fires. Instead of
* changing \FcsrIcountCount from 1 to 0, it is also acceptable for hardware to
- * clear \FcsrMcontrolM, \FcsrMcontrolS, and \FcsrMcontrolU. This allows \FcsrIcountCount to be hard-wired
+ * clear \FcsrIcountM, \FcsrIcountS, \FcsrIcountU, \FcsrIcountVs, and
+ * \FcsrIcountVu. This allows \FcsrIcountCount to be hard-wired
* to 1 if this register just exists for single step.
*/
#define CSR_ICOUNT_COUNT_OFFSET 10
#define CSR_ICOUNT_COUNT_LENGTH 14
#define CSR_ICOUNT_COUNT (0x3fffULL << CSR_ICOUNT_COUNT_OFFSET)
/*
- * When set, every instruction completed in or trap taken from
- * M-mode decrements \FcsrIcountCount by 1.
+ * When set, enable this trigger in M-mode.
*/
#define CSR_ICOUNT_M_OFFSET 9
#define CSR_ICOUNT_M_LENGTH 1
#define CSR_ICOUNT_M (0x1ULL << CSR_ICOUNT_M_OFFSET)
/*
- * When set, every instruction completed in or trap taken from
- * S-mode decrements \FcsrIcountCount by 1.
+ * This bit becomes set when \FcsrIcountCount is decremented from 1
+ * to 0. It is cleared when the trigger fires.
+ */
+#define CSR_ICOUNT_PENDING_OFFSET 8
+#define CSR_ICOUNT_PENDING_LENGTH 1
+#define CSR_ICOUNT_PENDING (0x1ULL << CSR_ICOUNT_PENDING_OFFSET)
+/*
+ * When set, enable this trigger in S/HS-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * S-mode.
*/
#define CSR_ICOUNT_S_OFFSET 7
#define CSR_ICOUNT_S_LENGTH 1
#define CSR_ICOUNT_S (0x1ULL << CSR_ICOUNT_S_OFFSET)
/*
- * When set, every instruction completed in or trap taken from
- * U-mode decrements \FcsrIcountCount by 1.
+ * When set, enable this trigger in U-mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * U-mode.
*/
#define CSR_ICOUNT_U_OFFSET 6
#define CSR_ICOUNT_U_LENGTH 1
#define CSR_ITRIGGER_HIT_OFFSET (XLEN-6)
#define CSR_ITRIGGER_HIT_LENGTH 1
#define CSR_ITRIGGER_HIT (0x1ULL << CSR_ITRIGGER_HIT_OFFSET)
+/*
+ * When set, enable this trigger for interrupts that are taken from VS
+ * mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * virtualization mode.
+ */
+#define CSR_ITRIGGER_VS_OFFSET 12
+#define CSR_ITRIGGER_VS_LENGTH 1
+#define CSR_ITRIGGER_VS (0x1ULL << CSR_ITRIGGER_VS_OFFSET)
+/*
+ * When set, enable this trigger for interrupts that are taken from VU
+ * mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * virtualization mode.
+ */
+#define CSR_ITRIGGER_VU_OFFSET 11
+#define CSR_ITRIGGER_VU_LENGTH 1
+#define CSR_ITRIGGER_VU (0x1ULL << CSR_ITRIGGER_VU_OFFSET)
/*
* When set, enable this trigger for interrupts that are taken from M
* mode.
#define CSR_ITRIGGER_M_LENGTH 1
#define CSR_ITRIGGER_M (0x1ULL << CSR_ITRIGGER_M_OFFSET)
/*
- * When set, enable this trigger for interrupts that are taken from S
+ * When set, enable this trigger for interrupts that are taken from S/HS
* mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * S-mode.
*/
#define CSR_ITRIGGER_S_OFFSET 7
#define CSR_ITRIGGER_S_LENGTH 1
/*
* When set, enable this trigger for interrupts that are taken from U
* mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * U-mode.
*/
#define CSR_ITRIGGER_U_OFFSET 6
#define CSR_ITRIGGER_U_LENGTH 1
#define CSR_ETRIGGER_HIT_OFFSET (XLEN-6)
#define CSR_ETRIGGER_HIT_LENGTH 1
#define CSR_ETRIGGER_HIT (0x1ULL << CSR_ETRIGGER_HIT_OFFSET)
+/*
+ * When set, enable this trigger for exceptions that are taken from VS
+ * mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * virtualization mode.
+ */
+#define CSR_ETRIGGER_VS_OFFSET 12
+#define CSR_ETRIGGER_VS_LENGTH 1
+#define CSR_ETRIGGER_VS (0x1ULL << CSR_ETRIGGER_VS_OFFSET)
+/*
+ * When set, enable this trigger for exceptions that are taken from VU
+ * mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * virtualization mode.
+ */
+#define CSR_ETRIGGER_VU_OFFSET 11
+#define CSR_ETRIGGER_VU_LENGTH 1
+#define CSR_ETRIGGER_VU (0x1ULL << CSR_ETRIGGER_VU_OFFSET)
/*
* When set, non-maskable interrupts cause this
- * trigger to fire, regardless of the values of \FcsrMcontrolM, \FcsrMcontrolS, and \FcsrMcontrolU.
+ * trigger to fire, regardless of the values of \FcsrEtriggerM, \FcsrEtriggerS, and \FcsrEtriggerU.
*/
#define CSR_ETRIGGER_NMI_OFFSET 10
#define CSR_ETRIGGER_NMI_LENGTH 1
#define CSR_ETRIGGER_M_LENGTH 1
#define CSR_ETRIGGER_M (0x1ULL << CSR_ETRIGGER_M_OFFSET)
/*
- * When set, enable this trigger for exceptions that are taken from S
+ * When set, enable this trigger for exceptions that are taken from S/HS
* mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * S-mode.
*/
#define CSR_ETRIGGER_S_OFFSET 7
#define CSR_ETRIGGER_S_LENGTH 1
/*
* When set, enable this trigger for exceptions that are taken from U
* mode.
+ * This bit is hard-wired to 0 if the hart does not support
+ * U-mode.
*/
#define CSR_ETRIGGER_U_OFFSET 6
#define CSR_ETRIGGER_U_LENGTH 1
#define CSR_ETRIGGER_ACTION_OFFSET 0
#define CSR_ETRIGGER_ACTION_LENGTH 6
#define CSR_ETRIGGER_ACTION (0x3fULL << CSR_ETRIGGER_ACTION_OFFSET)
+#define CSR_TMEXTTRIGGER 0x7a1
+#define CSR_TMEXTTRIGGER_TYPE_OFFSET (XLEN-4)
+#define CSR_TMEXTTRIGGER_TYPE_LENGTH 4
+#define CSR_TMEXTTRIGGER_TYPE (0xfULL << CSR_TMEXTTRIGGER_TYPE_OFFSET)
+#define CSR_TMEXTTRIGGER_DMODE_OFFSET (XLEN-5)
+#define CSR_TMEXTTRIGGER_DMODE_LENGTH 1
+#define CSR_TMEXTTRIGGER_DMODE (0x1ULL << CSR_TMEXTTRIGGER_DMODE_OFFSET)
+/*
+ * If this bit is implemented, the hardware sets it when this
+ * trigger matches. The trigger's user can set or clear it at any
+ * time. It is used to determine which
+ * trigger(s) matched. If the bit is not implemented, it is always 0
+ * and writing it has no effect.
+ */
+#define CSR_TMEXTTRIGGER_HIT_OFFSET (XLEN-6)
+#define CSR_TMEXTTRIGGER_HIT_LENGTH 1
+#define CSR_TMEXTTRIGGER_HIT (0x1ULL << CSR_TMEXTTRIGGER_HIT_OFFSET)
+/*
+ * This optional bit, when set, causes this trigger to fire whenever an attached
+ * interrupt controller signals a trigger.
+ */
+#define CSR_TMEXTTRIGGER_INTCTL_OFFSET 22
+#define CSR_TMEXTTRIGGER_INTCTL_LENGTH 1
+#define CSR_TMEXTTRIGGER_INTCTL (0x1ULL << CSR_TMEXTTRIGGER_INTCTL_OFFSET)
+/*
+ * Selects any combination of up to 16 external debug trigger inputs
+ * that cause this trigger to fire.
+ */
+#define CSR_TMEXTTRIGGER_SELECT_OFFSET 6
+#define CSR_TMEXTTRIGGER_SELECT_LENGTH 16
+#define CSR_TMEXTTRIGGER_SELECT (0xffffULL << CSR_TMEXTTRIGGER_SELECT_OFFSET)
+/*
+ * The action to take when the trigger fires. The values are explained
+ * in Table~\ref{tab:action}.
+ */
+#define CSR_TMEXTTRIGGER_ACTION_OFFSET 0
+#define CSR_TMEXTTRIGGER_ACTION_LENGTH 6
+#define CSR_TMEXTTRIGGER_ACTION (0x3fULL << CSR_TMEXTTRIGGER_ACTION_OFFSET)
#define CSR_TEXTRA32 0x7a3
/*
- * Data used together with \FcsrTextraThirtytwoMselect.
+ * Data used together with \FcsrTextraThirtytwoMhselect.
*/
-#define CSR_TEXTRA32_MVALUE_OFFSET 26
-#define CSR_TEXTRA32_MVALUE_LENGTH 6
-#define CSR_TEXTRA32_MVALUE (0x3fU << CSR_TEXTRA32_MVALUE_OFFSET)
+#define CSR_TEXTRA32_MHVALUE_OFFSET 26
+#define CSR_TEXTRA32_MHVALUE_LENGTH 6
+#define CSR_TEXTRA32_MHVALUE (0x3fU << CSR_TEXTRA32_MHVALUE_OFFSET)
/*
- * 0: Ignore \FcsrTextraThirtytwoMvalue.
+ * 0: Ignore \FcsrTextraThirtytwoMhvalue.
*
- * 1: This trigger will only match if the low bits of
- * \RcsrMcontext equal \FcsrTextraThirtytwoMvalue.
+ * 4: This trigger will only match if the low bits of
+ * \RcsrMcontext/\RcsrHcontext equal \FcsrTextraThirtytwoMhvalue.
+ *
+ * 1, 5: This trigger will only match if the low bits of
+ * \RcsrMcontext/\RcsrHcontext equal \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}.
+ *
+ * 2, 6: This trigger will only match if VMID in hgatp equals the lower VMIDMAX
+ * (defined in the Privileged Spec) bits of \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}.
+ *
+ * 3, 7: Reserved.
+ *
+ * If the H extension is not supported, the only legal values are 0 and 4.
+ */
+#define CSR_TEXTRA32_MHSELECT_OFFSET 23
+#define CSR_TEXTRA32_MHSELECT_LENGTH 3
+#define CSR_TEXTRA32_MHSELECT (0x7U << CSR_TEXTRA32_MHSELECT_OFFSET)
+/*
+ * When the least significant bit of this field is 1, it causes bits 7:0
+ * in the comparison to be ignored, when \FcsrTextraThirtytwoSselect=1.
+ * When the next most significant bit of this field is 1, it causes bits 15:8
+ * to be ignored in the comparison, when \FcsrTextraThirtytwoSselect=1.
*/
-#define CSR_TEXTRA32_MSELECT_OFFSET 25
-#define CSR_TEXTRA32_MSELECT_LENGTH 1
-#define CSR_TEXTRA32_MSELECT (0x1U << CSR_TEXTRA32_MSELECT_OFFSET)
+#define CSR_TEXTRA32_SBYTEMASK_OFFSET 18
+#define CSR_TEXTRA32_SBYTEMASK_LENGTH 2
+#define CSR_TEXTRA32_SBYTEMASK (0x3U << CSR_TEXTRA32_SBYTEMASK_OFFSET)
/*
* Data used together with \FcsrTextraThirtytwoSselect.
*
* 1: This trigger will only match if the low bits of
* \RcsrScontext equal \FcsrTextraThirtytwoSvalue.
*
- * 2: This trigger will only match if \Fasid in \Rsatp
+ * 2: This trigger will only match if the currently active ASID
+ * value, from either \Rsatp or \Rvsatp,
* equals the lower ASIDMAX (defined in the Privileged Spec) bits of
* \FcsrTextraThirtytwoSvalue.
*
#define CSR_TEXTRA32_SSELECT_LENGTH 2
#define CSR_TEXTRA32_SSELECT (0x3U << CSR_TEXTRA32_SSELECT_OFFSET)
#define CSR_TEXTRA64 0x7a3
-#define CSR_TEXTRA64_MVALUE_OFFSET 51
-#define CSR_TEXTRA64_MVALUE_LENGTH 13
-#define CSR_TEXTRA64_MVALUE (0x1fffULL << CSR_TEXTRA64_MVALUE_OFFSET)
-#define CSR_TEXTRA64_MSELECT_OFFSET 50
-#define CSR_TEXTRA64_MSELECT_LENGTH 1
-#define CSR_TEXTRA64_MSELECT (0x1ULL << CSR_TEXTRA64_MSELECT_OFFSET)
+#define CSR_TEXTRA64_MHVALUE_OFFSET 51
+#define CSR_TEXTRA64_MHVALUE_LENGTH 13
+#define CSR_TEXTRA64_MHVALUE (0x1fffULL << CSR_TEXTRA64_MHVALUE_OFFSET)
+#define CSR_TEXTRA64_MHSELECT_OFFSET 48
+#define CSR_TEXTRA64_MHSELECT_LENGTH 3
+#define CSR_TEXTRA64_MHSELECT (0x7ULL << CSR_TEXTRA64_MHSELECT_OFFSET)
+/*
+ * When the least significant bit of this field is 1, it causes bits 7:0
+ * in the comparison to be ignored, when \FcsrTextraSixtyfourSselect=1.
+ * Likewise, the second bit controls the comparison of bits 15:8,
+ * third bit controls the comparison of bits 23:16,
+ * fourth bit controls the comparison of bits 31:24, and
+ * fifth bit controls the comparison of bits 33:32.
+ */
+#define CSR_TEXTRA64_SBYTEMASK_OFFSET 36
+#define CSR_TEXTRA64_SBYTEMASK_LENGTH 5
+#define CSR_TEXTRA64_SBYTEMASK (0x1fULL << CSR_TEXTRA64_SBYTEMASK_OFFSET)
#define CSR_TEXTRA64_SVALUE_OFFSET 2
#define CSR_TEXTRA64_SVALUE_LENGTH 34
#define CSR_TEXTRA64_SVALUE (0x3ffffffffULL << CSR_TEXTRA64_SVALUE_OFFSET)
#define CSR_TEXTRA64_SSELECT_LENGTH 2
#define CSR_TEXTRA64_SSELECT (0x3ULL << CSR_TEXTRA64_SSELECT_OFFSET)
#define DM_DMSTATUS 0x11
+/*
+ * 0: Unimplemented, or \FdmDmcontrolNdmreset is zero and no ndmreset is currently
+ * in progress.
+ *
+ * 1: \FdmDmcontrolNdmreset is currently nonzero, or there is an ndmreset in progress.
+ */
+#define DM_DMSTATUS_NDMRESETPENDING_OFFSET 24
+#define DM_DMSTATUS_NDMRESETPENDING_LENGTH 1
+#define DM_DMSTATUS_NDMRESETPENDING (0x1U << DM_DMSTATUS_NDMRESETPENDING_OFFSET)
+/*
+ * 0: The per-hart {\tt unavail} bits reflect the current state of the hart.
+ *
+ * 1: The per-hart {\tt unavail} bits are sticky. Once they are set, they will
+ * not clear until the debugger acknowledges them using \FdmDmcontrolAckunavail.
+ */
+#define DM_DMSTATUS_STICKYUNAVAIL_OFFSET 23
+#define DM_DMSTATUS_STICKYUNAVAIL_LENGTH 1
+#define DM_DMSTATUS_STICKYUNAVAIL (0x1U << DM_DMSTATUS_STICKYUNAVAIL_OFFSET)
/*
* If 1, then there is an implicit {\tt ebreak} instruction at the
* non-existent word immediately after the Program Buffer. This saves
#define DM_DMSTATUS_ANYRESUMEACK (0x1U << DM_DMSTATUS_ANYRESUMEACK_OFFSET)
/*
* This field is 1 when all currently selected harts do not exist in
- * this platform.
+ * this hardware platform.
*/
#define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 15
#define DM_DMSTATUS_ALLNONEXISTENT_LENGTH 1
#define DM_DMSTATUS_ALLNONEXISTENT (0x1U << DM_DMSTATUS_ALLNONEXISTENT_OFFSET)
/*
* This field is 1 when any currently selected hart does not exist in
- * this platform.
+ * this hardware platform.
*/
#define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 14
#define DM_DMSTATUS_ANYNONEXISTENT_LENGTH 1
#define DM_DMSTATUS_ANYNONEXISTENT (0x1U << DM_DMSTATUS_ANYNONEXISTENT_OFFSET)
/*
- * This field is 1 when all currently selected harts are unavailable.
+ * This field is 1 when all currently selected harts are
+ * unavailable, or (if \FdmDmstatusStickyunavail is 1) were
+ * unavailable without that being acknowledged.
*/
#define DM_DMSTATUS_ALLUNAVAIL_OFFSET 13
#define DM_DMSTATUS_ALLUNAVAIL_LENGTH 1
#define DM_DMSTATUS_ALLUNAVAIL (0x1U << DM_DMSTATUS_ALLUNAVAIL_OFFSET)
/*
- * This field is 1 when any currently selected hart is unavailable.
+ * This field is 1 when any currently selected hart is unavailable,
+ * or (if \FdmDmstatusStickyunavail is 1) was unavailable without
+ * that being acknowledged.
*/
#define DM_DMSTATUS_ANYUNAVAIL_OFFSET 12
#define DM_DMSTATUS_ANYUNAVAIL_LENGTH 1
* 2: There is a Debug Module and it conforms to version 0.13 of this
* specification.
*
- * 3: There is a Debug Module and it conforms to version 0.14 of this
+ * 3: There is a Debug Module and it conforms to version 1.0 of this
* specification.
*
* 15: There is a Debug Module but it does not conform to any
#define DM_DMCONTROL_ACKHAVERESET_OFFSET 28
#define DM_DMCONTROL_ACKHAVERESET_LENGTH 1
#define DM_DMCONTROL_ACKHAVERESET (0x1U << DM_DMCONTROL_ACKHAVERESET_OFFSET)
+/*
+ * 0: No effect.
+ *
+ * 1: Clears {\tt unavail} for any selected harts.
+ *
+ * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
+ */
+#define DM_DMCONTROL_ACKUNAVAIL_OFFSET 27
+#define DM_DMCONTROL_ACKUNAVAIL_LENGTH 1
+#define DM_DMCONTROL_ACKUNAVAIL (0x1U << DM_DMCONTROL_ACKUNAVAIL_OFFSET)
/*
* Selects the definition of currently selected harts.
*
#define DM_DMCONTROL_HARTSELHI_OFFSET 6
#define DM_DMCONTROL_HARTSELHI_LENGTH 10
#define DM_DMCONTROL_HARTSELHI (0x3ffU << DM_DMCONTROL_HARTSELHI_OFFSET)
+/*
+ * This optional field sets \Fkeepalive for all currently selected
+ * harts, unless \FdmDmcontrolClrkeepalive is simultaneously set to
+ * 1.
+ *
+ * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
+ */
+#define DM_DMCONTROL_SETKEEPALIVE_OFFSET 5
+#define DM_DMCONTROL_SETKEEPALIVE_LENGTH 1
+#define DM_DMCONTROL_SETKEEPALIVE (0x1U << DM_DMCONTROL_SETKEEPALIVE_OFFSET)
+/*
+ * This optional field clears \Fkeepalive for all currently selected
+ * harts.
+ *
+ * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
+ */
+#define DM_DMCONTROL_CLRKEEPALIVE_OFFSET 4
+#define DM_DMCONTROL_CLRKEEPALIVE_LENGTH 1
+#define DM_DMCONTROL_CLRKEEPALIVE (0x1U << DM_DMCONTROL_CLRKEEPALIVE_OFFSET)
/*
* This optional field writes the halt-on-reset request bit for all
* currently selected harts, unless \FdmDmcontrolClrresethaltreq is
#define DM_DMCONTROL_CLRRESETHALTREQ (0x1U << DM_DMCONTROL_CLRRESETHALTREQ_OFFSET)
/*
* This bit controls the reset signal from the DM to the rest of the
- * system. The signal should reset every part of the system, including
+ * hardware platform. The signal should reset every part of the hardware platform, including
* every hart, except for the DM and any logic required to access the
* DM.
- * To perform a system reset the debugger writes 1,
+ * To perform a hardware platform reset the debugger writes 1,
* and then writes 0
* to deassert the reset.
*/
#define DM_DMCONTROL_NDMRESET (0x1U << DM_DMCONTROL_NDMRESET_OFFSET)
/*
* This bit serves as a reset signal for the Debug Module itself.
+ * After changing the value of this bit, the debugger must poll
+ * \RdmDmcontrol until \FdmDmcontrolDmactive has taken the requested value
+ * before performing any action that assumes the requested \FdmDmcontrolDmactive
+ * state change has completed. Hardware may
+ * take an arbitrarily long time to complete activation or deactivation and will
+ * indicate completion by setting \FdmDmcontrolDmactive to the requested value.
*
* 0: The module's state, including authentication mechanism,
* takes its reset values (the \FdmDmcontrolDmactive bit is the only bit which can
* be written to something other than its reset value). Any accesses
- * to the module may fail. Specifically, \FdmDmstatusVersion may not return
+ * to the module may fail. Specifically, \FdmDmstatusVersion might not return
* correct data.
*
- * 1: The module functions normally. After writing 1, the debugger should
- * poll \RdmDmcontrol until \FdmDmcontrolDmactive is high. Hardware may
- * take an arbitrarily long time to initialize and will indicate completion
- * by setting dmactive to 1.
+ * 1: The module functions normally.
*
* No other mechanism should exist that may result in resetting the
* Debug Module after power up.
*
- * A debugger may pulse this bit low to get the Debug Module into a
- * known state.
+ * To place the Debug Module into a known state, a debugger may write 0 to \FdmDmcontrolDmactive,
+ * poll until \FdmDmcontrolDmactive is observed 0, write 1 to \FdmDmcontrolDmactive, and
+ * poll until \FdmDmcontrolDmactive is observed 1.
*
* Implementations may pay attention to this bit to further aid
* debugging, for example by preventing the Debug Module from being
#define DM_HAWINDOWSEL 0x14
/*
* The high bits of this field may be tied to 0, depending on how large
- * the array mask register is. E.g.\ on a system with 48 harts only bit 0
+ * the array mask register is. E.g.\ on a hardware platform with 48 harts only bit 0
* of this field may actually be writable.
*/
#define DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0
#define DM_DATA0_DATA_OFFSET 0
#define DM_DATA0_DATA_LENGTH 32
#define DM_DATA0_DATA (0xffffffffU << DM_DATA0_DATA_OFFSET)
+#define DM_DATA1 0x05
+#define DM_DATA2 0x06
+#define DM_DATA3 0x07
+#define DM_DATA4 0x08
+#define DM_DATA5 0x09
+#define DM_DATA6 0x0a
+#define DM_DATA7 0x0b
+#define DM_DATA8 0x0c
+#define DM_DATA9 0x0d
+#define DM_DATA10 0x0e
#define DM_DATA11 0x0f
#define DM_PROGBUF0 0x20
#define DM_PROGBUF0_DATA_OFFSET 0
#define DM_PROGBUF0_DATA_LENGTH 32
#define DM_PROGBUF0_DATA (0xffffffffU << DM_PROGBUF0_DATA_OFFSET)
+#define DM_PROGBUF1 0x21
+#define DM_PROGBUF2 0x22
+#define DM_PROGBUF3 0x23
+#define DM_PROGBUF4 0x24
+#define DM_PROGBUF5 0x25
+#define DM_PROGBUF6 0x26
+#define DM_PROGBUF7 0x27
+#define DM_PROGBUF8 0x28
+#define DM_PROGBUF9 0x29
+#define DM_PROGBUF10 0x2a
+#define DM_PROGBUF11 0x2b
+#define DM_PROGBUF12 0x2c
+#define DM_PROGBUF13 0x2d
+#define DM_PROGBUF14 0x2e
#define DM_PROGBUF15 0x2f
#define DM_AUTHDATA 0x30
#define DM_AUTHDATA_DATA_OFFSET 0
#define DM_DMCS2_GROUPTYPE_LENGTH 1
#define DM_DMCS2_GROUPTYPE (0x1U << DM_DMCS2_GROUPTYPE_OFFSET)
/*
- * This field contains the currently selected external trigger.
+ * This field contains the currently selected DM external trigger.
*
* If a non-existent trigger value is written here, the hardware will
- * change it to a valid one or 0 if no external triggers exist.
+ * change it to a valid one or 0 if no DM external triggers exist.
*/
-#define DM_DMCS2_EXTTRIGGER_OFFSET 7
-#define DM_DMCS2_EXTTRIGGER_LENGTH 4
-#define DM_DMCS2_EXTTRIGGER (0xfU << DM_DMCS2_EXTTRIGGER_OFFSET)
+#define DM_DMCS2_DMEXTTRIGGER_OFFSET 7
+#define DM_DMCS2_DMEXTTRIGGER_LENGTH 4
+#define DM_DMCS2_DMEXTTRIGGER (0xfU << DM_DMCS2_DMEXTTRIGGER_OFFSET)
/*
* When \FdmDmcsTwoHgselect is 0, contains the group of the hart
* specified by \Fhartsel.
*
- * When \FdmDmcsTwoHgselect is 1, contains the group of the external
- * trigger selected by \FdmDmcsTwoExttrigger.
+ * When \FdmDmcsTwoHgselect is 1, contains the group of the DM external
+ * trigger selected by \FdmDmcsTwoDmexttrigger.
*
* Writes only have an effect if \FdmDmcsTwoHgwrite is also written 1.
*
#define DM_DMCS2_GROUP_LENGTH 5
#define DM_DMCS2_GROUP (0x1fU << DM_DMCS2_GROUP_OFFSET)
/*
- * When \FdmDmcsTwoHgselect is 0, writing 1 changes the group of all
- * selected harts to the value written to \FdmDmcsTwoGroup.
- *
* When 1 is written and \FdmDmcsTwoHgselect is 0, for every selected
* hart the DM will change its group to the value written to \FdmDmcsTwoGroup,
* if the hardware supports that group for that hart.
+ * Implementations may also change the group of a minimal set of
+ * unselected harts in the same way, if that is necessary due to
+ * a hardware limitation.
*
* When 1 is written and \FdmDmcsTwoHgselect is 1, the DM will change
- * the group of the external trigger selected by \FdmDmcsTwoExttrigger
+ * the group of the DM external trigger selected by \FdmDmcsTwoDmexttrigger
* to the value written to \FdmDmcsTwoGroup, if the hardware supports
* that group for that trigger.
*
/*
* 0: Operate on harts.
*
- * 1: Operate on external triggers.
+ * 1: Operate on DM external triggers.
*
- * If there are no external triggers, this field must be tied to 0.
+ * If there are no DM external triggers, this field must be tied to 0.
*/
#define DM_DMCS2_HGSELECT_OFFSET 0
#define DM_DMCS2_HGSELECT_LENGTH 1
#define DM_SBDATA3_DATA (0xffffffffU << DM_SBDATA3_DATA_OFFSET)
#define DM_CUSTOM 0x1f
#define DM_CUSTOM0 0x70
+#define DM_CUSTOM1 0x71
+#define DM_CUSTOM2 0x72
+#define DM_CUSTOM3 0x73
+#define DM_CUSTOM4 0x74
+#define DM_CUSTOM5 0x75
+#define DM_CUSTOM6 0x76
+#define DM_CUSTOM7 0x77
+#define DM_CUSTOM8 0x78
+#define DM_CUSTOM9 0x79
+#define DM_CUSTOM10 0x7a
+#define DM_CUSTOM11 0x7b
+#define DM_CUSTOM12 0x7c
+#define DM_CUSTOM13 0x7d
+#define DM_CUSTOM14 0x7e
#define DM_CUSTOM15 0x7f
#define SHORTNAME 0x123
/*
* 0: No effect. This variant must be supported.
*
* 1: After a successful register access, \FacAccessregisterRegno is
- * incremented (wrapping around to 0). Supporting this variant is
- * optional. It is undefined whether the increment happens when
- * \FacAccessregisterTransfer is 0.
+ * incremented. Incrementing past the highest supported value
+ * causes \FacAccessregisterRegno to become \unspecified. Supporting
+ * this variant is optional. It is undefined whether the increment
+ * happens when \FacAccessregisterTransfer is 0.
*/
#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 19
#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1
* 0: Addresses are physical (to the hart they are performed on).
*
* 1: Addresses are virtual, and translated the way they would be from
- * M-mode, with \FcsrMcontrolMprv set.
+ * M-mode, with \FcsrMstatusMprv set.
+ *
+ * Debug Modules on systems without address translation (i.e. virtual addresses equal physical)
+ * may optionally allow \FacAccessmemoryAamvirtual set to 1, which would produce the same result as
+ * that same abstract command with \FacAccessmemoryAamvirtual cleared.
*/
#define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 23
#define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1
#define AC_ACCESS_MEMORY_TARGET_SPECIFIC_LENGTH 2
#define AC_ACCESS_MEMORY_TARGET_SPECIFIC (0x3U << AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET)
#define VIRT_PRIV virtual
+/*
+ * Contains the virtualization mode the hart was operating in when Debug
+ * Mode was entered. The encoding is described in Table \ref{tab:privlevel},
+ * and matches the virtualization mode encoding from the Privileged Spec.
+ * A user can write this value to change the hart's virtualization mode
+ * when exiting Debug Mode.
+ */
+#define VIRT_PRIV_V_OFFSET 2
+#define VIRT_PRIV_V_LENGTH 1
+#define VIRT_PRIV_V (0x1U << VIRT_PRIV_V_OFFSET)
/*
* Contains the privilege level the hart was operating in when Debug
* Mode was entered. The encoding is described in Table
Code Review / openocd.git / blobdiff