uint16_t address, uint64_t data)
{
riscv011_info_t *info = get_info(target);
+ RISCV_INFO(r);
+
+ if (r->reset_delays_wait >= 0) {
+ r->reset_delays_wait--;
+ if (r->reset_delays_wait < 0) {
+ info->dbus_busy_delay = 0;
+ info->interrupt_high_delay = 0;
+ }
+ }
field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
field->in_value = in_value;
LOG_DEBUG("enter");
- struct breakpoint *breakpoint = target->breakpoints;
- while (breakpoint) {
- riscv_remove_breakpoint(target, breakpoint);
- breakpoint = breakpoint->next;
- }
-
struct watchpoint *watchpoint = target->watchpoints;
while (watchpoint) {
riscv_remove_watchpoint(target, watchpoint);
if (result != ERROR_OK)
return result;
- breakpoint = target->breakpoints;
- while (breakpoint) {
- riscv_add_breakpoint(target, breakpoint);
- breakpoint = breakpoint->next;
- }
-
watchpoint = target->watchpoints;
while (watchpoint) {
riscv_add_watchpoint(target, watchpoint);
if (result != ERROR_OK)
return result;
} else {
- return resume(target, 0, true);
+ return full_step(target, false);
}
return ERROR_OK;
break;
default:
LOG_ERROR("Got invalid bus access status: %d", status);
- return ERROR_FAIL;
+ goto error;
}
if (data & DMCONTROL_INTERRUPT) {
interrupt_set++;
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case DCSR_CAUSE_HWBP:
- target->debug_reason = DBG_REASON_WPTANDBKPT;
+ target->debug_reason = DBG_REASON_WATCHPOINT;
/* If we halted because of a data trigger, gdb doesn't know to do
* the disable-breakpoints-step-enable-breakpoints dance. */
info->need_strict_step = true;