#include "target_type.h"
#include "armv7m.h"
#include "cortex_m.h"
+#include "arm_semihosting.h"
+
+#define ARMV7M_SCS_DCRSR 0xe000edf4
+#define ARMV7M_SCS_DCRDR 0xe000edf8
static inline struct stlink_interface_s *target_to_stlink(struct target *target)
{
LOG_ERROR("JTAG failure %i", retval);
return ERROR_JTAG_DEVICE_ERROR;
}
- LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",
- (int)num, *value);
+ LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
+ break;
+
+ case ARMV7M_FPSID:
+ case ARMV7M_FPEXC:
+ *value = 0;
+ break;
+
+ case ARMV7M_FPSCR:
+ /* Floating-point Status and Registers */
+ retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
+ break;
+
+ case ARMV7M_S0 ... ARMV7M_S31:
+ /* Floating-point Status and Registers */
+ retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
+ break;
+
+ case ARMV7M_D0 ... ARMV7M_D15:
+ value = 0;
break;
case ARMV7M_PRIMASK:
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
break;
+ case ARMV7M_FPSID:
+ case ARMV7M_FPEXC:
+ break;
+
+ case ARMV7M_FPSCR:
+ /* Floating-point Status and Registers */
+ retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
+ break;
+
+ case ARMV7M_S0 ... ARMV7M_S31:
+ /* Floating-point Status and Registers */
+ retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
+ break;
+
+ case ARMV7M_D0 ... ARMV7M_D15:
+ break;
+
case ARMV7M_PRIMASK:
case ARMV7M_BASEPRI:
case ARMV7M_FAULTMASK:
return ERROR_OK;
}
-static int stm32_stlink_examine(struct target *target)
-{
- int retval, i;
- uint32_t cpuid, fpcr;
- struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-
- LOG_DEBUG("%s", __func__);
-
- if (target->tap->hasidcode == false) {
- LOG_ERROR("no IDCODE present on device");
-
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- if (!target_was_examined(target)) {
- target_set_examined(target);
-
- LOG_INFO("IDCODE %x", target->tap->idcode);
-
- /* Read from Device Identification Registers */
- retval = target_read_u32(target, CPUID, &cpuid);
- if (retval != ERROR_OK)
- return retval;
-
- if (((cpuid >> 4) & 0xc3f) == 0xc23)
- LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
- (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
- LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
-
- /* Setup FPB */
- target_read_u32(target, FP_CTRL, &fpcr);
- cortex_m3->auto_bp_type = 1;
- cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) |
- ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
- cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
- cortex_m3->fp_code_available = cortex_m3->fp_num_code;
- cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code +
- cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
- cortex_m3->fpb_enabled = fpcr & 1;
- for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) {
- cortex_m3->fp_comparator_list[i].type =
- (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
- cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
- }
- LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr,
- cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
-
- /* Setup DWT */
- cortex_m3_dwt_setup(cortex_m3, target);
-
- /* These hardware breakpoints only work for code in flash! */
- LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
- target_name(target),
- cortex_m3->fp_num_code,
- cortex_m3->dwt_num_comp);
- }
-
- return ERROR_OK;
-}
-
static int stm32_stlink_load_context(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
armv7m->exception_number = 0;
}
- LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
+ LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
armv7m_mode_strings[armv7m->core_mode],
*(uint32_t *)(arm->pc->value),
target_state_name(target));
if (state == TARGET_HALTED) {
target->state = state;
- stlink_debug_entry(target);
+ int retval = stlink_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (arm_semihosting(target, &retval) != 0)
+ return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- LOG_DEBUG("halted: PC: 0x%x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
+ LOG_DEBUG("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
}
return ERROR_OK;
static int stm32_stlink_assert_reset(struct target *target)
{
- int res;
+ int res = ERROR_OK;
struct stlink_interface_s *stlink_if = target_to_stlink(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
+ bool use_srst_fallback = true;
LOG_DEBUG("%s", __func__);
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+ bool srst_asserted = false;
+
+ if (jtag_reset_config & RESET_SRST_NO_GATING) {
+ jtag_add_reset(0, 1);
+ res = stlink_if->layout->api->assert_srst(stlink_if->fd, 0);
+ srst_asserted = true;
+ }
+
+ stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN);
+ stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET);
+
+ if (jtag_reset_config & RESET_HAS_SRST) {
+ if (!srst_asserted) {
+ jtag_add_reset(0, 1);
+ res = stlink_if->layout->api->assert_srst(stlink_if->fd, 0);
+ }
+ if (res == ERROR_COMMAND_NOTFOUND)
+ LOG_ERROR("Hardware srst not supported, falling back to software reset");
+ else if (res == ERROR_OK) {
+ /* hardware srst supported */
+ use_srst_fallback = false;
+ }
+ }
+
+ if (use_srst_fallback) {
+ /* stlink v1 api does support hardware srst, so we use a software reset fallback */
+ stlink_if->layout->api->write_debug_reg(stlink_if->fd, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+ }
+
res = stlink_if->layout->api->reset(stlink_if->fd);
if (res != ERROR_OK)
return res;
- /* virtual assert reset, we need it for the internal
- * jtag state machine
- */
- jtag_add_reset(1, 1);
-
/* registers are now invalid */
register_cache_invalidate(armv7m->core_cache);
static int stm32_stlink_deassert_reset(struct target *target)
{
int res;
+ struct stlink_interface_s *stlink_if = target_to_stlink(target);
+
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
LOG_DEBUG("%s", __func__);
+ if (jtag_reset_config & RESET_HAS_SRST)
+ stlink_if->layout->api->assert_srst(stlink_if->fd, 1);
+
/* virtual deassert reset, we need it for the internal
* jtag state machine
*/
struct breakpoint *breakpoint = NULL;
struct reg *pc;
- LOG_DEBUG("%s %d %x %d %d", __func__, current, address,
+ LOG_DEBUG("%s %d 0x%08x %d %d", __func__, current, address,
handle_breakpoints, debug_execution);
if (target->state != TARGET_HALTED) {
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
- target->debug_reason = DBG_REASON_SINGLESTEP;
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-
stlink_debug_entry(target);
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- LOG_INFO("halted: PC: 0x%x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
+ LOG_INFO("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
return ERROR_OK;
}
int res;
uint32_t buffer_threshold = 128;
uint32_t addr_increment = 4;
- uint8_t *dst = buffer;
uint32_t c;
struct stlink_interface_s *stlink_if = target_to_stlink(target);
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
- LOG_DEBUG("%s %x %d %d", __func__, address, size, count);
+ LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count);
/* prepare byte count, buffer threshold
* and address increment for none 32bit access
if (size != 4)
res = stlink_if->layout->api->read_mem8(stlink_if->fd,
- address, c, dst);
+ address, c, buffer);
else
res = stlink_if->layout->api->read_mem32(stlink_if->fd,
- address, c, (uint32_t *)dst);
+ address, c, buffer);
if (res != ERROR_OK)
return res;
address += (c * addr_increment);
- dst += (c * addr_increment);
+ buffer += (c * addr_increment);
count -= c;
}
int res;
uint32_t buffer_threshold = 128;
uint32_t addr_increment = 4;
- const uint8_t *dst = buffer;
uint32_t c;
struct stlink_interface_s *stlink_if = target_to_stlink(target);
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
- LOG_DEBUG("%s %x %d %d", __func__, address, size, count);
+ LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count);
/* prepare byte count, buffer threshold
* and address increment for none 32bit access
if (size != 4)
res = stlink_if->layout->api->write_mem8(stlink_if->fd,
- address, c, dst);
+ address, c, buffer);
else
res = stlink_if->layout->api->write_mem32(stlink_if->fd,
- address, c, (uint32_t *)dst);
+ address, c, buffer);
if (res != ERROR_OK)
return res;
address += (c * addr_increment);
- dst += (c * addr_increment);
+ buffer += (c * addr_increment);
count -= c;
}
.init_target = stm32_stlink_init_target,
.target_create = stm32_stlink_target_create,
- .examine = stm32_stlink_examine,
+ .examine = cortex_m3_examine,
.poll = stm32_stlink_poll,
.arch_state = armv7m_arch_state,
Code Review / openocd.git / blobdiff