- int retval = ERROR_OK;
- target_t *target;
-
- target = all_targets;
-
- target_all_handle_event( TARGET_EVENT_OLD_pre_reset );
-
- if ((retval = jtag_init_reset(cmd_ctx)) != ERROR_OK)
- return retval;
-
- keep_alive(); /* we might be running on a very slow JTAG clk */
-
- /* First time this is executed after launching OpenOCD, it will read out
- * the type of CPU, etc. and init Embedded ICE registers in host
- * memory.
- *
- * It will also set up ICE registers in the target.
- *
- * However, if we assert TRST later, we need to set up the registers again.
- *
- * For the "reset halt/init" case we must only set up the registers here.
- */
- if ((retval = target_examine()) != ERROR_OK)
- return retval;
-
- keep_alive(); /* we might be running on a very slow JTAG clk */
-
- target = all_targets;
- while (target)
- {
- /* we have no idea what state the target is in, so we
- * have to drop working areas
- */
- target_free_all_working_areas_restore(target, 0);
- target->reset_halt=((reset_mode==RESET_HALT)||(reset_mode==RESET_INIT));
- if ((retval = target->type->assert_reset(target))!=ERROR_OK)
- return retval;
- target = target->next;
- }
-
- target = all_targets;
- while (target)
- {
- if ((retval = target->type->deassert_reset(target))!=ERROR_OK)
- return retval;
- target = target->next;
- }
-
- target = all_targets;
- while (target)
- {
- /* We can fail to bring the target into the halted state, try after reset has been deasserted */
- if (target->reset_halt)
- {
- /* wait up to 1 second for halt. */
- target_wait_state(target, TARGET_HALTED, 1000);
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("Failed to reset target into halted mode - issuing halt");
- if ((retval = target->type->halt(target))!=ERROR_OK)
- return retval;
- }
- }
-
- target = target->next;