#include "trace.h"
#include "image.h"
#include "rtos/rtos.h"
+#include "transport/transport.h"
/* default halt wait timeout (ms) */
#define DEFAULT_HALT_TIMEOUT 5000
extern struct target_type dragonite_target;
extern struct target_type xscale_target;
extern struct target_type cortexm_target;
-extern struct target_type cortexa8_target;
+extern struct target_type cortexa_target;
extern struct target_type cortexr4_target;
extern struct target_type arm11_target;
extern struct target_type mips_m4k_target;
&dragonite_target,
&xscale_target,
&cortexm_target,
- &cortexa8_target,
+ &cortexa_target,
&cortexr4_target,
&arm11_target,
&mips_m4k_target,
int retval;
int timeout = 0;
+ const uint8_t *buffer_orig = buffer;
+
/* Set up working area. First word is write pointer, second word is read pointer,
* rest is fifo data area. */
uint32_t wp_addr = buffer_start;
break;
}
- LOG_DEBUG("count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32, count, wp, rp);
+ LOG_DEBUG("offs 0x%zx count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32,
+ (buffer - buffer_orig), count, wp, rp);
if (rp == 0) {
LOG_ERROR("flash write algorithm aborted by target");
if (e != JIM_OK)
return e;
cp = cp2;
+ struct transport *tr = get_current_transport();
+ if (tr->override_target) {
+ e = tr->override_target(&cp);
+ if (e != ERROR_OK) {
+ LOG_ERROR("The selected transport doesn't support this target");
+ return JIM_ERR;
+ }
+ LOG_INFO("The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD");
+ }
/* now does target type exist */
for (x = 0 ; target_types[x] ; x++) {
if (0 == strcmp(cp, target_types[x]->name)) {
target = calloc(1, sizeof(struct target));
/* set target number */
target->target_number = new_target_number();
+ cmd_ctx->current_target = target->target_number;
/* allocate memory for each unique target type */
target->type = calloc(1, sizeof(struct target_type));