+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2011 Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "transport/transport.h"
#include "arm_cti.h"
#include "smp.h"
+#include "semihosting_common.h"
/* default halt wait timeout (ms) */
#define DEFAULT_HALT_TIMEOUT 5000
extern struct target_type feroceon_target;
extern struct target_type dragonite_target;
extern struct target_type xscale_target;
+extern struct target_type xtensa_chip_target;
extern struct target_type cortexm_target;
extern struct target_type cortexa_target;
extern struct target_type aarch64_target;
extern struct target_type nds32_v2_target;
extern struct target_type nds32_v3_target;
extern struct target_type nds32_v3m_target;
+extern struct target_type esp32_target;
+extern struct target_type esp32s2_target;
+extern struct target_type esp32s3_target;
extern struct target_type or1k_target;
extern struct target_type quark_x10xx_target;
extern struct target_type quark_d20xx_target;
&feroceon_target,
&dragonite_target,
&xscale_target,
+ &xtensa_chip_target,
&cortexm_target,
&cortexa_target,
&cortexr4_target,
&nds32_v2_target,
&nds32_v3_target,
&nds32_v3m_target,
+ &esp32_target,
+ &esp32s2_target,
+ &esp32s3_target,
&or1k_target,
&quark_x10xx_target,
&quark_d20xx_target,
* Disable polling during resume() to guarantee the execution of handlers
* in the correct order.
*/
- bool save_poll = jtag_poll_get_enabled();
- jtag_poll_set_enabled(false);
+ bool save_poll_mask = jtag_poll_mask();
retval = target->type->resume(target, current, address, handle_breakpoints, debug_execution);
- jtag_poll_set_enabled(save_poll);
+ jtag_poll_unmask(save_poll_mask);
+
if (retval != ERROR_OK)
return retval;
* more predictable, i.e. dr/irscan & pathmove in events will
* not have JTAG operations injected into the middle of a sequence.
*/
- bool save_poll = jtag_poll_get_enabled();
-
- jtag_poll_set_enabled(false);
+ bool save_poll_mask = jtag_poll_mask();
sprintf(buf, "ocd_process_reset %s", n->name);
retval = Jim_Eval(cmd->ctx->interp, buf);
- jtag_poll_set_enabled(save_poll);
+ jtag_poll_unmask(save_poll_mask);
if (retval != JIM_OK) {
Jim_MakeErrorMessage(cmd->ctx->interp);
struct working_area *new_wa = malloc(sizeof(*new_wa));
if (new_wa) {
new_wa->next = NULL;
- new_wa->size = target->working_area_size & ~3UL; /* 4-byte align */
+ new_wa->size = ALIGN_DOWN(target->working_area_size, 4); /* 4-byte align */
new_wa->address = target->working_area;
new_wa->backup = NULL;
new_wa->user = NULL;
}
/* only allocate multiples of 4 byte */
- if (size % 4)
- size = (size + 3) & (~3UL);
+ size = ALIGN_UP(size, 4);
struct working_area *c = target->working_areas;
uint32_t max_size = 0;
if (!c)
- return target->working_area_size;
+ return ALIGN_DOWN(target->working_area_size, 4);
while (c) {
if (c->free && max_size < c->size)
if (target->type->deinit_target)
target->type->deinit_target(target);
+ if (target->semihosting)
+ free(target->semihosting->basedir);
free(target->semihosting);
jtag_unregister_event_callback(jtag_enable_callback, target);
}
if (!target->type->blank_check_memory)
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ return ERROR_NOT_IMPLEMENTED;
return target->type->blank_check_memory(target, blocks, num_blocks, erased_value);
}
{
struct target *target = get_current_target(CMD_CTX);
- LOG_USER("requesting target halt and executing a soft reset");
+ LOG_TARGET_INFO(target, "requesting target halt and executing a soft reset");
target_soft_reset_halt(target);
int i;
const char *targetname;
int retval, len;
+ static int smp_group = 1;
struct target *target = NULL;
struct target_list *head, *new;
/* now parse the list of cpu and put the target in smp mode*/
foreach_smp_target(head, lh) {
target = head->target;
- target->smp = 1;
+ target->smp = smp_group;
target->smp_targets = lh;
}
+ smp_group++;
if (target && target->rtos)
retval = rtos_smp_init(target);