retired reset run_and_init/halt

[openocd.git] / src / target / target / str912.cfg

diff --git a/src/target/target/str912.cfg b/src/target/target/str912.cfg
index e827cdf037fffb52cd61bbfa5a64d2d4a287118e..c9bef81bc4948149dad66382ceb46e1de7fe689a 100644 (file)
--- a/src/target/target/str912.cfg
+++ b/src/target/target/str912.cfg
@@ -1,3 +1,27 @@
+# script for str9
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+
+jtag_khz 16
+proc target_0_pre_reset {} {
+       jtag_khz 16
+}
+
+proc target_0_post_reset {} {
+       # We can increase speed now that we know the target is halted.
+       jtag_khz 3000
+       
+       # -- Enable 96K RAM
+       # PFQBC enabled / DTCM & AHB wait-states disabled
+       mww 0x5C002034 0x0191 
+
+       str9x flash_config 0 4 2 0 0x80000
+       flash protect 0 0 7 off
+       
+       
+}
+
+
 jtag_nsrst_delay 100
 jtag_ntrst_delay 100
 
@@ -12,10 +36,9 @@ jtag_device 5 0x1 0x1 0x1e
 
 #target <type> <startup mode>
 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
-target arm966e little reset_halt 1 arm966e
-run_and_halt_time 0 30
+target arm966e little 1 arm966e
+
 
-target_script 0 reset event/str912_reset.script
 
 working_area 0 0x50000000 16384 nobackup