adi_v5_jtag: make sure SSTICKYERR is cleared after a POR
[openocd.git] / src / target / x86_32_common.h
index af57a5f7eefeca9bc6323a210ac1011e5599f4a8..b5877da4a10c400d4d752ff5737ff9807f1bdc2e 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright(c) 2013 Intel Corporation.
+ * Copyright(c) 2013-2016 Intel Corporation.
  *
  * Adrian Burns (adrian.burns@intel.com)
  * Thomas Faust (thomas.faust@intel.com)
@@ -18,8 +18,7 @@
  * General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  *
  * Contact Information:
  * Intel Corporation
@@ -30,8 +29,8 @@
  * This is the interface to the x86 32 bit memory and breakpoint operations.
  */
 
-#ifndef X86_32_COMMON_H
-#define X86_32_COMMON_H
+#ifndef OPENOCD_TARGET_X86_32_COMMON_H
+#define OPENOCD_TARGET_X86_32_COMMON_H
 
 #include <jtag/jtag.h>
 #include <helper/command.h>
@@ -196,6 +195,11 @@ enum {
        WBINVD,
 };
 
+enum x86_core_type {
+       LMT1,
+       LMT3_5
+};
+
 struct swbp_mem_patch {
        uint8_t orig_byte;
        uint32_t swbp_unique_id;
@@ -209,6 +213,7 @@ struct swbp_mem_patch {
 struct x86_32_common {
        uint32_t common_magic;
        void *arch_info;
+       enum x86_core_type core_type;
        struct reg_cache *cache;
        struct jtag_tap *curr_tap;
        uint32_t stored_pc;
@@ -322,4 +327,4 @@ int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp);
 int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp);
 int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp);
 
-#endif /* X86_32_COMMON_H */
+#endif /* OPENOCD_TARGET_X86_32_COMMON_H */

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