static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
{
- if (tap == NULL)
- return ERROR_FAIL;
+ assert (tap != NULL);
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t pc;
uint32_t buffer[10];
- int i;
+ unsigned i;
int retval;
uint32_t moe;
r->valid = true;
}
+ /* mark xscale regs invalid to ensure they are retrieved from the
+ * debug handler if requested */
+ for (i = 0; i < xscale->reg_cache->num_regs; i++)
+ xscale->reg_cache->reg_list[i].valid = 0;
+
/* examine debug reason */
xscale_read_dcsr(target);
moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
return retval;
+ LOG_ERROR("data abort writing memory");
return ERROR_TARGET_DATA_ABORT;
}
return xscale_write_memory(target, address, 4, count, buffer);
}
-static uint32_t xscale_get_ttb(struct target *target)
+static int xscale_get_ttb(struct target *target, uint32_t *result)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t ttb;
+ int retval;
- xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
+ retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
+ if (retval != ERROR_OK)
+ return retval;
ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
- return ttb;
+ *result = ttb;
+
+ return ERROR_OK;
}
-static void xscale_disable_mmu_caches(struct target *target, int mmu,
+static int xscale_disable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+ retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+ if (retval !=ERROR_OK)
+ return retval;
cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
if (mmu)
if (d_u_cache)
{
/* clean DCache */
- xscale_send_u32(target, 0x50);
- xscale_send_u32(target, xscale->cache_clean_address);
+ retval = xscale_send_u32(target, 0x50);
+ if (retval !=ERROR_OK)
+ return retval;
+ retval = xscale_send_u32(target, xscale->cache_clean_address);
+ if (retval !=ERROR_OK)
+ return retval;
/* invalidate DCache */
- xscale_send_u32(target, 0x51);
+ retval = xscale_send_u32(target, 0x51);
+ if (retval !=ERROR_OK)
+ return retval;
cp15_control &= ~0x4U;
}
if (i_cache)
{
/* invalidate ICache */
- xscale_send_u32(target, 0x52);
+ retval = xscale_send_u32(target, 0x52);
+ if (retval !=ERROR_OK)
+ return retval;
cp15_control &= ~0x1000U;
}
/* write new cp15 control register */
- xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+ retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+ if (retval !=ERROR_OK)
+ return retval;
/* execute cpwait to ensure outstanding operations complete */
- xscale_send_u32(target, 0x53);
+ retval = xscale_send_u32(target, 0x53);
+ return retval;
}
-static void xscale_enable_mmu_caches(struct target *target, int mmu,
+static int xscale_enable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+ retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+ if (retval !=ERROR_OK)
+ return retval;
cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
if (mmu)
cp15_control |= 0x1000U;
/* write new cp15 control register */
- xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+ retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+ if (retval !=ERROR_OK)
+ return retval;
/* execute cpwait to ensure outstanding operations complete */
- xscale_send_u32(target, 0x53);
+ retval = xscale_send_u32(target, 0x53);
+ return retval;
}
static int xscale_set_breakpoint(struct target *target,
breakpoint->set = 2; /* breakpoint set on second breakpoint register */
}
else
- {
+ { /* bug: availability previously verified in xscale_add_breakpoint() */
LOG_ERROR("BUG: no hardware comparator available");
- return ERROR_OK;
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
else if (breakpoint->type == BKPT_SOFT)
return retval;
}
/* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
- if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
+ if ((retval = target_write_u16(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
{
return retval;
}
if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
{
- LOG_INFO("no breakpoint unit available for hardware breakpoint");
+ LOG_ERROR("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((breakpoint->length != 2) && (breakpoint->length != 4))
{
- LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
+ LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
xscale->ibcr_available--;
}
- return ERROR_OK;
+ return xscale_set_breakpoint(target, breakpoint);
}
static int xscale_unset_breakpoint(struct target *target,
if (target->state != TARGET_HALTED)
{
- LOG_WARNING("target not halted");
+ LOG_ERROR("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (target->state != TARGET_HALTED)
{
- LOG_WARNING("target not halted");
+ LOG_ERROR("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (xscale->dbr_available < 1)
{
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ LOG_ERROR("no more watchpoint registers available");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (watchpoint->value)
/* watchpoints across multiple words require both DBR registers */
if (xscale->dbr_available < 2)
+ {
+ LOG_ERROR("insufficient watchpoint registers available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
xscale->dbr_available = 0;
return ERROR_OK;
if (target->state != TARGET_HALTED)
{
- LOG_WARNING("target not halted");
+ LOG_ERROR("target not halted");
return ERROR_TARGET_NOT_HALTED;
}