static int xscale_arch_state(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
static const char *state[] =
{
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+ buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[xscale->armv4_5_mmu.mmu_enabled],
state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
static int xscale_debug_entry(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t pc;
uint32_t buffer[10];
int i;
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
}
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+ arm_set_cpsr(armv4_5, buffer[9]);
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
- armv4_5->core_mode = buffer[9] & 0x1f;
if (!is_arm_mode(armv4_5->core_mode))
{
target->state = TARGET_UNKNOWN;
LOG_DEBUG("target entered debug state in %s mode",
arm_mode_name(armv4_5->core_mode));
- if (buffer[9] & 0x20)
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
- else
- armv4_5->core_state = ARMV4_5_STATE_ARM;
-
-
/* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
{
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc;
int retval;
xscale_send_u32(target, 0x30);
/* send CPSR */
- xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
- LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+ xscale_send_u32(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
+ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--)
{
xscale_send_u32(target, 0x30);
/* send CPSR */
- xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
- LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+ xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32));
+ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--)
{
uint32_t address, int handle_breakpoints)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t next_pc;
int retval;
int i;
return retval;
/* send CPSR */
- if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
+ retval = xscale_send_u32(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
+ if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--)
{
static int xscale_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc;
static int xscale_full_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
uint32_t *buffer;
static int xscale_restore_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
int i, j;
static int xscale_read_trace(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
struct xscale_trace_data **trace_data_p;
/* 258 words from debug handler
static void xscale_build_reg_cache(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
int i;
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t dcsr_value;
int retval;
return ERROR_OK;
}
+static const struct command_registration xscale_exec_command_handlers[] = {
+ {
+ .name = "cache_info",
+ .handler = &xscale_handle_cache_info_command,
+ .mode = COMMAND_EXEC, NULL,
+ },
+
+ {
+ .name = "mmu",
+ .handler = &xscale_handle_mmu_command,
+ .mode = COMMAND_EXEC,
+ .usage = "[enable|disable]",
+ .help = "enable or disable the MMU",
+ },
+ {
+ .name = "icache",
+ .handler = &xscale_handle_idcache_command,
+ .mode = COMMAND_EXEC,
+ .usage = "[enable|disable]",
+ .help = "enable or disable the ICache",
+ },
+ {
+ .name = "dcache",
+ .handler = &xscale_handle_idcache_command,
+ .mode = COMMAND_EXEC,
+ .usage = "[enable|disable]",
+ .help = "enable or disable the DCache",
+ },
+
+ {
+ .name = "vector_catch",
+ .handler = &xscale_handle_vector_catch_command,
+ .mode = COMMAND_EXEC,
+ .help = "mask of vectors that should be caught",
+ .usage = "[<mask>]",
+ },
+ {
+ .name = "vector_table",
+ .handler = &xscale_handle_vector_table_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<high|low> <index> <code>",
+ .help = "set static code for exception handler entry",
+ },
+
+ {
+ .name = "trace_buffer",
+ .handler = &xscale_handle_trace_buffer_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<enable | disable> [fill [n]|wrap]",
+ },
+ {
+ .name = "dump_trace",
+ .handler = &xscale_handle_dump_trace_command,
+ .mode = COMMAND_EXEC,
+ .help = "dump content of trace buffer to <file>",
+ .usage = "<file>",
+ },
+ {
+ .name = "analyze_trace",
+ .handler = &xscale_handle_analyze_trace_buffer_command,
+ .mode = COMMAND_EXEC,
+ .help = "analyze content of trace buffer",
+ },
+ {
+ .name = "trace_image",
+ .handler = &xscale_handle_trace_image_command,
+ COMMAND_EXEC,
+ .help = "load image from <file> [base address]",
+ .usage = "<file> [address] [type]",
+ },
+
+ {
+ .name = "cp15",
+ .handler = &xscale_handle_cp15,
+ .mode = COMMAND_EXEC,
+ .help = "access coproc 15",
+ .usage = "<register> [value]",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration xscale_any_command_handlers[] = {
+ {
+ .name = "debug_handler",
+ .handler = &xscale_handle_debug_handler_command,
+ .mode = COMMAND_ANY,
+ .usage = "<target#> <address>",
+ },
+ {
+ .name = "cache_clean_address",
+ .handler = &xscale_handle_cache_clean_address_command,
+ .mode = COMMAND_ANY,
+ },
+ {
+ .chain = xscale_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration xscale_command_handlers[] = {
+ {
+ .name = "xscale",
+ .mode = COMMAND_ANY,
+ .help = "xscale command group",
+ .chain = xscale_any_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
static int xscale_register_commands(struct command_context *cmd_ctx)
{
- struct command *xscale_cmd;
-
- xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
-
- register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
- register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
-
- register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
- register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
- register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
- register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
-
- register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
- register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, "<high|low> <index> <code> set static code for exception handler entry");
-
- register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
-
- register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
- register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
- register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
- COMMAND_EXEC, "load image from <file> [base address]");
-
- register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
armv4_5_register_commands(cmd_ctx);
Code Review / openocd.git / blobdiff