return ERROR_OK;
}
-static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr)
+static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
{
if (tap == NULL)
return ERROR_FAIL;
uint8_t scratch[4];
memset(&field, 0, sizeof field);
- field.tap = tap;
field.num_bits = tap->ir_length;
field.out_value = scratch;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
- jtag_add_ir_scan(1, &field, jtag_get_end_state());
+ jtag_add_ir_scan(tap, &field, end_state);
}
return ERROR_OK;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
- jtag_set_end_state(TAP_DRPAUSE);
xscale_jtag_set_instr(target->tap,
- XSCALE_SELDCSR << xscale->xscale_variant);
+ XSCALE_SELDCSR << xscale->xscale_variant,
+ TAP_DRPAUSE);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL;
- jtag_set_end_state(TAP_IDLE);
-
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
/* DANGER!!! this must be here. It will make sure that the arguments
* to jtag_set_check_value() does not go out of scope! */
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].check_value = &field0_check_value;
fields[0].check_mask = &field0_check_mask;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].check_value = &field2_check_value;
fields[2].check_mask = &field2_check_mask;
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_DBGTX << xscale->xscale_variant);
- jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
+ XSCALE_DBGTX << xscale->xscale_variant,
+ TAP_IDLE);
+ jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
/* repeat until all words have been collected */
int attempts = 0;
fields[1].in_value = (uint8_t *)(field1 + i);
- jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
- jtag_set_end_state(TAP_IDLE);
-
xscale_jtag_set_instr(target->tap,
- XSCALE_DBGTX << xscale->xscale_variant);
+ XSCALE_DBGTX << xscale->xscale_variant,
+ TAP_IDLE);
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].in_value = &field0_in;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
uint8_t tmp;
fields[2].in_value = &tmp;
jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
}
- jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
- jtag_set_end_state(TAP_IDLE);
-
xscale_jtag_set_instr(target->tap,
- XSCALE_DBGRX << xscale->xscale_variant);
+ XSCALE_DBGRX << xscale->xscale_variant,
+ TAP_IDLE);
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[0].in_value = &field0_in;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp;
LOG_DEBUG("polling RX");
for (;;)
{
- jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
/* set rx_valid */
field2 = 0x1;
- jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
int retval;
int done_count = 0;
- jtag_set_end_state(TAP_IDLE);
-
xscale_jtag_set_instr(target->tap,
- XSCALE_DBGRX << xscale->xscale_variant);
+ XSCALE_DBGRX << xscale->xscale_variant,
+ TAP_IDLE);
bits[0]=3;
t[0]=0;
3,
bits,
t,
- jtag_set_end_state(TAP_IDLE));
+ TAP_IDLE);
buffer += size;
}
if (ext_dbg_brk != -1)
xscale->external_debug_break = ext_dbg_brk;
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_SELDCSR << xscale->xscale_variant);
+ XSCALE_SELDCSR << xscale->xscale_variant,
+ TAP_IDLE);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
- fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
- fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
- jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
/* LDIC into IR */
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_LDIC << xscale->xscale_variant);
+ XSCALE_LDIC << xscale->xscale_variant,
+ TAP_IDLE);
/* CMD is b011 to load a cacheline into the Mini ICache.
* Loading into the main ICache is deprecated, and unused.
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
- fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
- jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
/* rest of packet is a cacheline: 8 instructions, with parity */
fields[0].num_bits = 32;
memcpy(&value, packet, sizeof(uint32_t));
cmd = parity(value);
- jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
}
return jtag_execute_queue();
uint8_t cmd;
struct scan_field fields[2];
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_LDIC << xscale->xscale_variant);
+ XSCALE_LDIC << xscale->xscale_variant,
+ TAP_IDLE);
/* CMD for invalidate IC line b000, bits [6:4] b000 */
buf_set_u32(&cmd, 0, 6, 0x0);
memset(&fields, 0, sizeof fields);
- fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
- fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
- jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
return ERROR_OK;
}
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_SELDCSR << xscale->xscale_variant);
+ XSCALE_SELDCSR << xscale->xscale_variant,
+ TAP_IDLE);
/* set Hold reset, Halt mode and Trap Reset */
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
- xscale_jtag_set_instr(target->tap, ~0);
+ xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
jtag_execute_queue();
/* assert reset */
/* wait 300ms; 150 and 100ms were not enough */
jtag_add_sleep(300*1000);
- jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE));
+ jtag_add_runtest(2030, TAP_IDLE);
jtag_execute_queue();
/* set Hold reset, Halt mode and Trap Reset */
if (retval != ERROR_OK)
return retval;
- jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE));
+ jtag_add_runtest(30, TAP_IDLE);
jtag_add_sleep(100000);
return ERROR_OK;
}
- bool icache;
- COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache");
-
+ bool icache = false;
+ if (strcmp(CMD_NAME, "icache") == 0)
+ icache = true;
if (CMD_ARGC >= 1)
{
bool enable;
COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
- if (enable)
- xscale_enable_mmu_caches(target, 1, 0, 0);
- else
- xscale_disable_mmu_caches(target, 1, 0, 0);
- if (icache)
+ if (icache) {
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
- else
+ if (enable)
+ xscale_enable_mmu_caches(target, 0, 0, 1);
+ else
+ xscale_disable_mmu_caches(target, 0, 0, 1);
+ } else {
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
+ if (enable)
+ xscale_enable_mmu_caches(target, 0, 1, 0);
+ else
+ xscale_disable_mmu_caches(target, 0, 1, 0);
+ }
}
bool enabled = icache ?
if (CMD_ARGC >= 2)
{
xscale->trace.image->base_address_set = 1;
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], xscale->trace.image->base_address);
+ COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
}
else
{