return ERROR_OK;
}
-static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr)
+static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
{
if (tap == NULL)
return ERROR_FAIL;
field.out_value = scratch;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
- jtag_add_ir_scan(tap, &field, jtag_get_end_state());
+ jtag_add_ir_scan(tap, &field, end_state);
}
return ERROR_OK;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
- jtag_set_end_state(TAP_DRPAUSE);
xscale_jtag_set_instr(target->tap,
- XSCALE_SELDCSR << xscale->xscale_variant);
+ XSCALE_SELDCSR << xscale->xscale_variant,
+ TAP_DRPAUSE);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL;
- jtag_set_end_state(TAP_IDLE);
-
jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
/* DANGER!!! this must be here. It will make sure that the arguments
fields[2].check_value = &field2_check_value;
fields[2].check_mask = &field2_check_mask;
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_DBGTX << xscale->xscale_variant);
+ XSCALE_DBGTX << xscale->xscale_variant,
+ TAP_IDLE);
jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
/* repeat until all words have been collected */
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
- jtag_set_end_state(TAP_IDLE);
-
xscale_jtag_set_instr(target->tap,
- XSCALE_DBGTX << xscale->xscale_variant);
+ XSCALE_DBGTX << xscale->xscale_variant,
+ TAP_IDLE);
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
uint8_t field2_check_value = 0x0;
uint8_t field2_check_mask = 0x1;
- jtag_set_end_state(TAP_IDLE);
-
xscale_jtag_set_instr(target->tap,
- XSCALE_DBGRX << xscale->xscale_variant);
+ XSCALE_DBGRX << xscale->xscale_variant,
+ TAP_IDLE);
memset(&fields, 0, sizeof fields);
int retval;
int done_count = 0;
- jtag_set_end_state(TAP_IDLE);
-
xscale_jtag_set_instr(target->tap,
- XSCALE_DBGRX << xscale->xscale_variant);
+ XSCALE_DBGRX << xscale->xscale_variant,
+ TAP_IDLE);
bits[0]=3;
t[0]=0;
if (ext_dbg_brk != -1)
xscale->external_debug_break = ext_dbg_brk;
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_SELDCSR << xscale->xscale_variant);
+ XSCALE_SELDCSR << xscale->xscale_variant,
+ TAP_IDLE);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
/* LDIC into IR */
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_LDIC << xscale->xscale_variant);
+ XSCALE_LDIC << xscale->xscale_variant,
+ TAP_IDLE);
/* CMD is b011 to load a cacheline into the Mini ICache.
* Loading into the main ICache is deprecated, and unused.
uint8_t cmd;
struct scan_field fields[2];
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_LDIC << xscale->xscale_variant);
+ XSCALE_LDIC << xscale->xscale_variant,
+ TAP_IDLE);
/* CMD for invalidate IC line b000, bits [6:4] b000 */
buf_set_u32(&cmd, 0, 6, 0x0);
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
- jtag_set_end_state(TAP_IDLE);
xscale_jtag_set_instr(target->tap,
- XSCALE_SELDCSR << xscale->xscale_variant);
+ XSCALE_SELDCSR << xscale->xscale_variant,
+ TAP_IDLE);
/* set Hold reset, Halt mode and Trap Reset */
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
- xscale_jtag_set_instr(target->tap, ~0);
+ xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
jtag_execute_queue();
/* assert reset */
{
bool enable;
COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
- if (enable)
- xscale_enable_mmu_caches(target, 1, 0, 0);
- else
- xscale_disable_mmu_caches(target, 1, 0, 0);
- if (icache)
+ if (icache) {
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
- else
+ if (enable)
+ xscale_enable_mmu_caches(target, 0, 0, 1);
+ else
+ xscale_disable_mmu_caches(target, 0, 0, 1);
+ } else {
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
+ if (enable)
+ xscale_enable_mmu_caches(target, 0, 1, 0);
+ else
+ xscale_disable_mmu_caches(target, 0, 1, 0);
+ }
}
bool enabled = icache ?